mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 11:42:30 +00:00
dbc38d72cf
Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
10 lines
149 B
Verilog
10 lines
149 B
Verilog
module test(input A, B, C, D, E,
|
|
output reg Y);
|
|
always @* begin
|
|
Y <= A;
|
|
if (B)
|
|
Y <= C;
|
|
if (D)
|
|
Y <= E;
|
|
end
|
|
endmodule
|