mirror of
https://github.com/YosysHQ/yosys
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dbc38d72cf
Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
8 lines
142 B
Verilog
8 lines
142 B
Verilog
module uut(in1, in2, in3, out1, out2);
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input [8:0] in1, in2, in3;
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output [8:0] out1, out2;
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assign out1 = in1 + in2 + (in3 >> 4);
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endmodule
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