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https://github.com/YosysHQ/yosys
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dbc38d72cf
Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
14 lines
300 B
Verilog
14 lines
300 B
Verilog
module scrambler(
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input clk, rst, in_bit,
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output reg out_bit
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);
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reg [31:0] xs;
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always @(posedge clk) begin
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if (rst)
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xs = 1;
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xs = xs ^ (xs << 13);
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xs = xs ^ (xs >> 17);
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xs = xs ^ (xs << 5);
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out_bit <= in_bit ^ xs[0];
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end
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endmodule
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