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90 lines
No EOL
1.3 KiB
Text
90 lines
No EOL
1.3 KiB
Text
#start:The following commands are executed by this synthesis command:
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#end:blif:
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begin:
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read_verilog -D ICE40_HX -lib -specify +/ice40/cells_sim.v
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hierarchy -check -top <top>
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proc
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flatten:
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flatten
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tribuf -logic
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deminout
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coarse:
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opt_expr
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opt_clean
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check
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opt -nodffe -nosdff
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fsm
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opt
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wreduce
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peepopt
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opt_clean
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share
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techmap
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opt_expr
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opt_clean
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memory_dff
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wreduce t:$mul
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techmap
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select a:mul2dsp
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setattr -unset mul2dsp
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opt_expr -fine
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wreduce
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select -clear
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ice40_dsp
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chtype -set $mul t:$__soft_mul
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alumacc
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opt
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memory -nomap [-no-rw-check]
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opt_clean
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map_ram:
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memory_libmap
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techmap
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ice40_braminit
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map_ffram:
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opt -fast -mux_undef -undriven -fine
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memory_map
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opt -undriven -fine
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map_gates:
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ice40_wrapcarry
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techmap
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opt -fast
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abc -dff -D 1
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ice40_opt
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map_ffs:
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dfflegalize
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techmap
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opt_expr -mux_undef
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simplemap
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ice40_opt -full
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map_luts:
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abc
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ice40_opt
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techmap
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simplemap
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techmap
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flowmap
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read_verilog
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abc9
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ice40_wrapcarry -unwrap
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techmap
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clean
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opt_lut -tech ice40
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map_cells:
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techmap
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clean
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check:
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autoname
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hierarchy -check
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stat
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check -noinit
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blackbox =A:whitebox
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