mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 11:42:30 +00:00
dbc38d72cf
Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
27 lines
674 B
Verilog
27 lines
674 B
Verilog
module axis_master(aclk, aresetn, tvalid, tready, tdata);
|
|
input aclk, aresetn, tready;
|
|
output reg tvalid;
|
|
output reg [7:0] tdata;
|
|
|
|
reg [31:0] state;
|
|
always @(posedge aclk) begin
|
|
if (!aresetn) begin
|
|
state <= 314159265;
|
|
tvalid <= 0;
|
|
tdata <= 'bx;
|
|
end else begin
|
|
if (tvalid && tready)
|
|
tvalid <= 0;
|
|
if (!tvalid || !tready) begin
|
|
// ^- should not be inverted!
|
|
state = state ^ state << 13;
|
|
state = state ^ state >> 7;
|
|
state = state ^ state << 17;
|
|
if (state[9:8] == 0) begin
|
|
tvalid <= 1;
|
|
tdata <= state;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
endmodule
|