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Code
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b5ecbbef94
yosys
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techlibs
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xilinx
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tests
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Marcin Kościelnicki
7e0e42f907
xilinx: Add simulation model for DSP48 (Virtex 4).
2020-01-29 01:40:00 +01:00
..
.gitignore
bram1.sh
bram1.v
bram1_tb.v
bram2.sh
bram2.v
bram2_tb.v
test_dsp48_model.sh
test_dsp48_model.v
test_dsp48a1_model.sh
test_dsp48a1_model.v
test_dsp_model.sh
test_dsp_model.v