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65 lines
613 B
Verilog
Executable file
65 lines
613 B
Verilog
Executable file
`timescale 1ns/1ns
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module tb_dlatchsr();
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reg d = 0;
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reg set = 0;
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reg clr = 0;
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wire q;
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dlatchsr uut(.d(d),.set(set),.clr(clr),.q(q));
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initial
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begin
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$dumpfile("tb_dlatchsr");
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$dumpvars(0,tb_dlatchsr);
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#10
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d = 1;
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#10
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d = 0;
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#10
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d = 1;
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#10
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d = 0;
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#10
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clr = 1;
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#10
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d = 1;
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#10
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d = 0;
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#10
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d = 1;
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#10
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d = 0;
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#10
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clr = 0;
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#10
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d = 1;
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#10
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d = 0;
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#10
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d = 1;
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#10
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d = 0;
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#10
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set = 1;
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#10
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d = 1;
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#10
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d = 0;
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#10
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d = 1;
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#10
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d = 0;
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#10
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set = 0;
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#10
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d = 1;
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#10
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d = 0;
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#10
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d = 1;
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#10
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d = 0;
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#10
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$finish;
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end
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endmodule
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