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https://github.com/YosysHQ/yosys
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375 lines
7.2 KiB
Verilog
375 lines
7.2 KiB
Verilog
// Copyright 2020-2022 F4PGA Authors
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// SPDX-License-Identifier: Apache-2.0
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`timescale 1ps/1ps
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`default_nettype none
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(* abc9_lut=1 *)
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module LUT1(output wire O, input wire I0);
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parameter [1:0] INIT = 0;
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assign O = I0 ? INIT[1] : INIT[0];
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specify
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(I0 => O) = 74;
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endspecify
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endmodule
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(* abc9_lut=2 *)
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module LUT2(output wire O, input wire I0, I1);
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parameter [3:0] INIT = 0;
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wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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specify
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(I0 => O) = 116;
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(I1 => O) = 74;
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endspecify
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endmodule
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(* abc9_lut=3 *)
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module LUT3(output wire O, input wire I0, I1, I2);
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parameter [7:0] INIT = 0;
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wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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specify
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(I0 => O) = 162;
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(I1 => O) = 116;
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(I2 => O) = 174;
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endspecify
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endmodule
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(* abc9_lut=3 *)
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module LUT4(output wire O, input wire I0, I1, I2, I3);
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parameter [15:0] INIT = 0;
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wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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specify
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(I0 => O) = 201;
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(I1 => O) = 162;
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(I2 => O) = 116;
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(I3 => O) = 74;
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endspecify
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endmodule
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(* abc9_lut=3 *)
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module LUT5(output wire O, input wire I0, I1, I2, I3, I4);
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parameter [31:0] INIT = 0;
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wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
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wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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specify
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(I0 => O) = 228;
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(I1 => O) = 189;
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(I2 => O) = 143;
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(I3 => O) = 100;
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(I4 => O) = 55;
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endspecify
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endmodule
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(* abc9_lut=5 *)
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module LUT6(output wire O, input wire I0, I1, I2, I3, I4, I5);
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parameter [63:0] INIT = 0;
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wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
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wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0];
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wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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specify
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(I0 => O) = 251;
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(I1 => O) = 212;
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(I2 => O) = 166;
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(I3 => O) = 123;
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(I4 => O) = 77;
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(I5 => O) = 43;
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endspecify
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endmodule
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(* abc9_flop, lib_whitebox *)
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module sh_dff(
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output reg Q,
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input wire D,
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(* clkbuf_sink *)
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input wire C
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);
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initial Q = 1'b0;
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always @(posedge C)
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Q <= D;
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specify
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(posedge C => (Q +: D)) = 0;
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$setuphold(posedge C, D, 0, 0);
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endspecify
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endmodule
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(* abc9_box, lib_whitebox *)
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(* keep *)
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module adder_carry(
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output wire sumout,
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(* abc9_carry *)
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output wire cout,
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input wire p,
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input wire g,
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(* abc9_carry *)
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input wire cin
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);
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assign sumout = p ^ cin;
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assign cout = p ? cin : g;
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specify
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(p => sumout) = 35;
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(g => sumout) = 35;
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(cin => sumout) = 40;
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(p => cout) = 67;
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(g => cout) = 65;
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(cin => cout) = 69;
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endspecify
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endmodule
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(* abc9_flop, lib_whitebox *)
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module dff(
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output reg Q,
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input wire D,
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(* clkbuf_sink *)
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input wire C
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);
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initial Q = 1'b0;
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always @(posedge C)
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Q <= D;
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specify
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(posedge C=>(Q+:D)) = 285;
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$setuphold(posedge C, D, 56, 0);
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endspecify
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endmodule
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(* abc9_flop, lib_whitebox *)
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module dffn(
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output reg Q,
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input wire D,
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(* clkbuf_sink *)
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input wire C
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);
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initial Q = 1'b0;
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always @(negedge C)
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Q <= D;
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specify
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(negedge C=>(Q+:D)) = 285;
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$setuphold(negedge C, D, 56, 0);
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endspecify
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endmodule
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(* abc9_flop, lib_whitebox *)
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module dffsre(
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output reg Q,
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input wire D,
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(* clkbuf_sink *)
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input wire C,
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input wire E,
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input wire R,
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input wire S
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);
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initial Q = 1'b0;
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always @(posedge C or negedge S or negedge R)
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if (!R)
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Q <= 1'b0;
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else if (!S)
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Q <= 1'b1;
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else if (E)
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Q <= D;
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specify
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(posedge C => (Q +: D)) = 280;
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(R => Q) = 0;
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(S => Q) = 0;
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$setuphold(posedge C, D, 56, 0);
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$setuphold(posedge C, E, 32, 0);
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$setuphold(posedge C, R, 0, 0);
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$setuphold(posedge C, S, 0, 0);
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$recrem(posedge R, posedge C, 0, 0);
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$recrem(posedge S, posedge C, 0, 0);
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endspecify
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endmodule
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(* abc9_flop, lib_whitebox *)
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module dffnsre(
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output reg Q,
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input wire D,
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(* clkbuf_sink *)
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input wire C,
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input wire E,
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input wire R,
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input wire S
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);
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initial Q = 1'b0;
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always @(negedge C or negedge S or negedge R)
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if (!R)
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Q <= 1'b0;
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else if (!S)
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Q <= 1'b1;
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else if (E)
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Q <= D;
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specify
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(negedge C => (Q +: D)) = 280;
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(R => Q) = 0;
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(S => Q) = 0;
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$setuphold(negedge C, D, 56, 0);
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$setuphold(negedge C, E, 32, 0);
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$setuphold(negedge C, R, 0, 0);
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$setuphold(negedge C, S, 0, 0);
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$recrem(posedge R, negedge C, 0, 0);
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$recrem(posedge S, negedge C, 0, 0);
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endspecify
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endmodule
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(* abc9_flop, lib_whitebox *)
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module sdffsre(
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output reg Q,
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input wire D,
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(* clkbuf_sink *)
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input wire C,
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input wire E,
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input wire R,
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input wire S
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);
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initial Q = 1'b0;
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always @(posedge C)
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if (!R)
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Q <= 1'b0;
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else if (!S)
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Q <= 1'b1;
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else if (E)
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Q <= D;
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specify
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(posedge C => (Q +: D)) = 280;
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$setuphold(posedge C, D, 56, 0);
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$setuphold(posedge C, R, 32, 0);
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$setuphold(posedge C, S, 0, 0);
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$setuphold(posedge C, E, 0, 0);
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endspecify
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endmodule
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(* abc9_flop, lib_whitebox *)
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module sdffnsre(
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output reg Q,
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input wire D,
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(* clkbuf_sink *)
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input wire C,
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input wire E,
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input wire R,
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input wire S
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);
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initial Q = 1'b0;
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always @(negedge C)
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if (!R)
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Q <= 1'b0;
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else if (!S)
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Q <= 1'b1;
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else if (E)
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Q <= D;
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specify
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(negedge C => (Q +: D)) = 280;
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$setuphold(negedge C, D, 56, 0);
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$setuphold(negedge C, R, 32, 0);
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$setuphold(negedge C, S, 0, 0);
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$setuphold(negedge C, E, 0, 0);
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endspecify
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endmodule
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(* abc9_flop, lib_whitebox *)
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module latchsre (
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output reg Q,
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input wire S,
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input wire R,
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input wire D,
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input wire G,
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input wire E
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);
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initial Q = 1'b0;
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always @*
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begin
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if (!R)
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Q <= 1'b0;
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else if (!S)
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Q <= 1'b1;
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else if (E && G)
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Q <= D;
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end
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specify
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(posedge G => (Q +: D)) = 0;
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$setuphold(posedge G, D, 0, 0);
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$setuphold(posedge G, E, 0, 0);
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$setuphold(posedge G, R, 0, 0);
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$setuphold(posedge G, S, 0, 0);
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endspecify
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endmodule
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(* abc9_flop, lib_whitebox *)
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module latchnsre (
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output reg Q,
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input wire S,
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input wire R,
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input wire D,
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input wire G,
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input wire E
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);
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initial Q = 1'b0;
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always @*
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begin
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if (!R)
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Q <= 1'b0;
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else if (!S)
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Q <= 1'b1;
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else if (E && !G)
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Q <= D;
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end
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specify
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(negedge G => (Q +: D)) = 0;
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$setuphold(negedge G, D, 0, 0);
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$setuphold(negedge G, E, 0, 0);
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$setuphold(negedge G, R, 0, 0);
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$setuphold(negedge G, S, 0, 0);
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endspecify
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endmodule
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