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yosys/frontends
2014-07-31 14:11:39 +02:00
..
ast Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
ilang Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
liberty Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
verific Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
verilog Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
vhdl2verilog Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00