mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-03 21:09:12 +00:00
134 lines
2.7 KiB
Text
134 lines
2.7 KiB
Text
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This file contains checklists for various tasks.
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Table of contents
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=================
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1. Checklist for creating Yosys releases
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2. Checklist for adding internal cell types
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1. Checklist for creating Yosys releases
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========================================
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Update the CHANGELOG file:
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cd ~yosys
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gitk &
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vi CHANGELOG
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Run all tests with "make config-{clang-debug,gcc-debug,gcc-4.7,release}":
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cd ~yosys
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make clean
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make test vloghtb
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make install
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cd ~yosys-bigsim
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make clean
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make full
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cd ~vloghammer
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make purge
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make gen_issues gen_samples
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make SYN_LIST="yosys" SIM_LIST="icarus yosim verilator" FULL=1 world
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chromium-browser report.html
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Then with default config setting:
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cd ~yosys
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./yosys -p 'proc; show' tests/simple/fiedler-cooley.v
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./yosys -p 'proc; opt; show' tests/simple/fiedler-cooley.v
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cd ~yosys
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make manual
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- sanity check the figures in the appnotes and presentation
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- if there are any odd things -> investigate
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- make cosmetic changes to the .tex files if necessary
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Also with default config setting:
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cd ~yosys/techlibs/cmos
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bash testbench.sh
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cd ~yosys/techlibs/xilinx/example_sim_counter
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bash run_sim.sh
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cd ~yosys/techlibs/xilinx/example_mojo_counter
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bash example.sh
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Finally if a current verific library is available:
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cd ~yosys
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cat frontends/verific/build_amd64.txt
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- follow instructions
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cd frontends/verific
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../../yosys test_navre.ys
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Release candiate:
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- create branch yosys-x.y.z-rc and push to github
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- contact the usual suspects per mail and ask them to test
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- post on the reddit and ask people to test
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- commit KISS fixes to the -rc branch if necessary
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Release:
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- set YOSYS_VER to x.y.z in Makefile
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- update version string in CHANGELOG
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git commit -am "Yosys x.y.z"
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- push tag to github
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- post changelog on github
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- post short release note on reddit
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- delete -rc branch from github
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Updating the website:
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cd ~yosys
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make manual
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make install
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- update pdf files on the website
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cd ~yosys-web
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make update_cmd
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make update_show
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git commit -am update
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make push
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In master branch:
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git merge {release-tag}
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- set version to x.y.z+ in Makefile
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- add section "Yosys x.y.z .. x.y.z+" to CHANGELOG
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git commit --amend -am "Yosys x.y.z+"
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2. Checklist for adding internal cell types
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===========================================
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Things to do right away:
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- Add to kernel/celltypes.h (incl. eval() handling for non-mem cells)
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- Add to InternalCellChecker::check() in kernel/rtlil.cc
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- Add to techlibs/common/simlib.v
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- Add to techlibs/common/techmap.v
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Things to do after finalizing the cell interface:
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- Add support to kernel/satgen.h for the new cell type
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- Add to manual/CHAPTER_CellLib.tex (or just add a fixme to the bottom)
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- Maybe add support to the verilog backend for dumping such cells as expression
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