mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 13:29:12 +00:00
18806f1ef6
Also properly skip read ports with init value or reset when not making use of make_outreg. Proper support for matching those will land later.
39 lines
1.4 KiB
Text
39 lines
1.4 KiB
Text
read_verilog ../common/lutram.v
|
|
hierarchy -top lutram_1w1r
|
|
proc
|
|
memory -nomap
|
|
equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram -noiopad -noclkbuf
|
|
memory
|
|
opt -full
|
|
|
|
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
|
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
|
|
|
|
design -load postopt
|
|
cd lutram_1w1r
|
|
select -assert-count 16 t:MISTRAL_MLAB
|
|
select -assert-count 2 t:MISTRAL_ALUT2
|
|
select -assert-count 8 t:MISTRAL_ALUT3
|
|
select -assert-count 8 t:MISTRAL_FF
|
|
select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
|
|
|
|
|
|
design -reset
|
|
read_verilog ../common/lutram.v
|
|
hierarchy -top lutram_1w1r
|
|
proc
|
|
memory -nomap
|
|
equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram -noiopad -noclkbuf
|
|
memory
|
|
opt -full
|
|
|
|
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
|
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
|
|
|
|
design -load postopt
|
|
cd lutram_1w1r
|
|
select -assert-count 16 t:MISTRAL_MLAB
|
|
select -assert-count 2 t:MISTRAL_ALUT2
|
|
select -assert-count 8 t:MISTRAL_ALUT3
|
|
select -assert-count 8 t:MISTRAL_FF
|
|
select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
|