Claire Wolf b597f85b13 Merge pull request #1718 from boqwxp/precise_locations ... Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.		2020-03-03 08:38:32 -08:00
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anlogic	Call equiv_opt with -multiclock and -assert	2019-12-31 18:39:32 -08:00
common	Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram	2019-12-16 21:48:21 -08:00
ecp5	Update bug1630.ys to use -lut 4 instead of lut file	2020-02-27 10:17:29 -08:00
efinix	Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux	2020-02-05 10:47:31 -08:00
gowin	Add opt_lut_ins pass. (#1673)	2020-02-03 14:57:17 +01:00
ice40	Change attribute search value to specify precise location instead of simple line number.	2020-02-24 02:41:08 +00:00
xilinx	Revert "Fix tests/arch/xilinx/fsm.ys to count flops only"	2020-02-27 10:17:29 -08:00
run-test.sh	Add simcells.v, simlib.v, and some output	2019-06-27 11:13:49 -07:00