mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 13:29:12 +00:00
Code Activity
yosys/techlibs/gowin
History
YRabbit b3f7f0d8dc Gowin. Disable unsupported BSRAM mode in GW5A 
All supported (and planned to be supported) GW5A series chips do not
support the 2: Read-before-Write write mode.

Here, we prohibit the generation of BSRAM with this mode.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-10-21 12:36:06 +10:00
..
arith_map.v gowin: Fix X output of $alu techmap 2023-05-01 17:56:41 +02:00
brams.txt gowin: Change BYTE ENABLE handling. 2024-01-27 17:19:49 +10:00
brams_gw5a.txt Gowin. Disable unsupported BSRAM mode in GW5A 2025-10-21 12:36:06 +10:00
brams_map.v gowin: Fix SDP write enable port. 2024-01-30 17:06:59 +10:00
brams_map_gw5a.v Gowin. Reduce the range of flip-flop types. 2025-10-11 21:12:35 +10:00
cells_map.v iopadmap: Add native support for negative-polarity output enable. 2021-11-09 15:40:16 +01:00
cells_sim.v Gowin. Renaming inputs of the DCS primitive. 2025-09-20 16:22:23 +01:00
cells_xtra.py Gowin. Renaming inputs of the DCS primitive. 2025-09-20 16:22:23 +01:00
cells_xtra_gw1n.v Gowin. Renaming inputs of the DCS primitive. 2025-09-20 16:22:23 +01:00
cells_xtra_gw2a.v Gowin. Renaming inputs of the DCS primitive. 2025-09-20 16:22:23 +01:00
cells_xtra_gw5a.v Gowin. Renaming inputs of the DCS primitive. 2025-09-20 16:22:23 +01:00
lutrams.txt gowin: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
lutrams_map.v gowin: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Makefile.inc Gowin. Disable unsupported BSRAM mode in GW5A 2025-10-21 12:36:06 +10:00
synth_gowin.cc Gowin. Disable unsupported BSRAM mode in GW5A 2025-10-21 12:36:06 +10:00