mirror of
https://github.com/YosysHQ/yosys
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87 lines
2.6 KiB
C++
87 lines
2.6 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2022 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/mem.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct MemoryBmux2RomPass : public Pass {
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MemoryBmux2RomPass() : Pass("memory_bmux2rom", "convert muxes to ROMs") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" memory_bmux2rom [options] [selection]\n");
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log("\n");
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log("This pass converts $bmux cells with constant A input to ROMs.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules()) {
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for (auto cell : module->selected_cells()) {
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if (cell->type != ID($bmux))
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continue;
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SigSpec sig_a = cell->getPort(ID::A);
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if (!sig_a.is_fully_const())
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continue;
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int abits = cell->getParam(ID::S_WIDTH).as_int();
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int width = cell->getParam(ID::WIDTH).as_int();
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if (abits < 3)
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continue;
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// Ok, let's do it.
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Mem mem(module, NEW_ID, width, 0, 1 << abits);
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mem.attributes = cell->attributes;
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MemInit init;
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init.addr = 0;
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init.data = sig_a.as_const();
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init.en = Const(State::S1, width);
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mem.inits.push_back(std::move(init));
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MemRd rd;
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rd.addr = cell->getPort(ID::S);
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rd.data = cell->getPort(ID::Y);
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rd.init_value = Const(State::Sx, width);
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rd.arst_value = Const(State::Sx, width);
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rd.srst_value = Const(State::Sx, width);
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mem.rd_ports.push_back(std::move(rd));
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mem.emit();
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module->remove(cell);
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}
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}
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}
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} MemoryBmux2RomPass;
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PRIVATE_NAMESPACE_END
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