mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-05 13:56:04 +00:00
d6b9158fa3
- consistently use value semantics for objects passed along FFI boundary (not ideal but matches previous behavior) - add new overload of RTLIL::Module: addMemory that does not require a "donor" object - the idea is `Module`, `Memory`, `Wire`, `Cell` and `Process` cannot be directly constructed in Python and can only be added to the existing memory hierarchy in `Design` using the `add` methods - `Memory` requiring a donor object was the odd one out here - fix superclass member wrapping only looking at direct superclass for inheritance instead of recursively checking superclasses - fix superclass member wrapping not using superclass's denylists - fix Design's `__str__` function not returning a string - fix the generator crashing if there's any `std::function` in a header - misc: add a crude `__repr__` based on `__str__` |
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| .. | ||
| run_tests.py | ||
| spm.cut.v.gz | ||
| test_data_read.py | ||
| test_dict.py | ||
| test_idict.py | ||
| test_idstring_lifetime.py | ||
| test_import.py | ||
| test_indirect_inheritance.py | ||
| test_logs.py | ||
| test_monitor.py | ||
| test_pass.py | ||
| test_script.py | ||
| test_set.py | ||