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.gitignore
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abc9_dff.ys
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ast: Use better parameter serialization for paramod names.
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2021-03-18 00:52:00 +01:00 |
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add_sub.ys
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xilinx: Initial support for LUT4 devices.
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2020-02-07 09:03:22 +01:00 |
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adffs.ys
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attributes_test.ys
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xilinx: Fix attributes_test.ys
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2020-10-24 23:52:37 +02:00 |
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blockram.ys
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bug1460.ys
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bug1462.ys
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bug1480.ys
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Cleanup tests
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2020-02-27 10:17:29 -08:00 |
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bug1598.ys
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bug1605.ys
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counter.ys
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dffs.ys
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abc9_ops: -reintegrate to use derived_type for box_ports
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2020-02-05 14:46:48 -08:00 |
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dsp_abc9.ys
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xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)
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2020-09-23 09:15:24 -07:00 |
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dsp_cascade.ys
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dsp_fastfir.ys
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dsp_simd.ys
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fsm.ys
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FfData: some refactoring.
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2021-10-07 04:24:06 +02:00 |
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latches.ys
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opt_expr: Remove -clkinv option, make it the default.
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2020-07-31 00:08:15 +02:00 |
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logic.ys
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lutram.ys
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xilinx: Add support for LUT RAM on LUT4-based devices.
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2020-02-07 09:03:22 +01:00 |
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macc.sh
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macc.v
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tests: xilinx macc test to have initval, shorten BMC depth for runtime
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2020-05-25 10:09:05 -07:00 |
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macc.ys
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tests: xilinx macc test to have initval, shorten BMC depth for runtime
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2020-05-25 10:09:05 -07:00 |
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macc_tb.v
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mul.ys
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mul_unsigned.v
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mul_unsigned.ys
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mux.ys
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xilinx_dffopt: Don't crash on missing IS_*_INVERTED.
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2021-01-27 00:32:00 +01:00 |
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mux_lut4.ys
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xilinx: Initial support for LUT4 devices.
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2020-02-07 09:03:22 +01:00 |
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nosrl.ys
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xilinx: Fix srl regression.
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2020-07-12 23:41:27 +02:00 |
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opt_lut_ins.ys
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pmgen_xilinx_srl.ys
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satgen: Add support for dffe, sdff, sdffe, sdffce cells.
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2020-07-24 03:19:21 +02:00 |
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run-test.sh
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tests: Centralize test collection and Makefile generation
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2020-09-21 15:07:02 +02:00 |
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shifter.ys
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tribuf.sh
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Fix the tests we just broke
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2021-12-10 00:22:37 +01:00 |
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tribuf.ys
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xilinx_dffopt.ys
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xilinx_dffopt: Don't crash on missing IS_*_INVERTED.
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2021-01-27 00:32:00 +01:00 |
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xilinx_dffopt_blacklist.txt
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xilinx_dsp.ys
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tests: read +/xilinx/cell_sim.v before xilinx_dsp test
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2020-04-22 17:50:30 -07:00 |
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xilinx_srl.v
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tests: fix some test warnings
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2020-05-25 10:07:58 -07:00 |
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xilinx_srl.ys
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