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yosys/frontends
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Zachary Snow b2e9717419 sv: support declaration in generate for initialization 
This is accomplished by generating a unique name for the genvar,
renaming references to the genvar only in the loop's initialization,
guard, and incrementation, and finally adding a localparam inside the
loop body with the original name so that the genvar can be shadowed as
expected.
2021-08-31 12:34:55 -06:00
..
aiger Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
ast Generate an RTLIL representation of bind constructs 2021-08-13 17:11:35 -06:00
blif Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
json Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
liberty Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
rpc Fix argument handling in connect_rpc 2020-10-19 13:40:57 +02:00
rtlil rtlil: Make Process handling more uniform with Cell and Wire. 2021-07-12 00:47:34 +02:00
verific Make Verific extensions optional 2021-08-20 10:19:04 +02:00
verilog sv: support declaration in generate for initialization 2021-08-31 12:34:55 -06:00