mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
bdc43c6592
for signed attributes Co-authored-by: N. Engelhardt <nak@yosyshq.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
18 lines
327 B
VHDL
18 lines
327 B
VHDL
library IEEE;
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
use IEEE.NUMERIC_STD.ALL;
|
|
|
|
entity work is
|
|
Port (
|
|
a : in INTEGER range -5 to 10;
|
|
b : out INTEGER range -6 to 11
|
|
);
|
|
end entity work;
|
|
|
|
architecture Behavioral of work is
|
|
begin
|
|
process(a)
|
|
begin
|
|
b <= a;
|
|
end process;
|
|
end architecture Behavioral;
|