YRabbit c37db637c7 Gowin. Remove unnecessary modules ... Primitives that are not planned for implementation for reasons of belonging to old unsupported chips or representing composite complex IPs rather than primitives are removed. Also latches and large MUXes not planned for implementation. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>		2025-03-28 06:34:26 +10:00
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achronix	techlibs: fix typo in help message	2023-11-13 16:29:52 +13:00
anlogic	Fix some synth_* help messages	2024-03-18 11:33:18 +13:00
common	Make all vector-size related integer params in $print sim model signed	2025-03-25 13:08:49 +00:00
coolrunner2	Blackbox all whiteboxes after synthesis	2021-03-17 21:07:20 +00:00
easic	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
ecp5	Fix some synth_* help messages	2024-03-18 11:33:18 +13:00
efinix	Merge pull request #4285 from YosysHQ/typo_fixup	2024-04-25 09:54:48 +12:00
fabulous	Fix some synth_* help messages	2024-03-18 11:33:18 +13:00
gatemate	gatemate: Add CC_SERDES parameters and update port names	2025-01-10 10:25:10 +01:00
gowin	Gowin. Remove unnecessary modules	2025-03-28 06:34:26 +10:00
greenpak4	rtlil: represent Const strings as std::string	2024-10-14 06:28:12 +02:00
ice40	pmgen: Move passes out of pmgen folder	2025-01-31 15:18:28 +13:00
intel	Removed SystemVerilog module end label	2024-03-19 01:31:36 +01:00
intel_alm	intel_alm: drop quartus support	2024-05-03 11:32:33 +01:00
lattice	Fix some synth_* help messages	2024-03-18 11:33:18 +13:00
microchip	pmgen: Move passes out of pmgen folder	2025-01-31 15:18:28 +13:00
nanoxplore	Cleanup of synth_nanoxplore pass	2024-09-03 10:15:50 +02:00
nexus	Fix some synth_* help messages	2024-03-18 11:33:18 +13:00
quicklogic	create duplicate IOFFs if multiple output ports are connected to the same register	2025-01-31 11:28:57 +01:00
sf2	Test fixes for latest iverilog	2022-09-21 15:46:43 +02:00
xilinx	pmgen: Move passes out of pmgen folder	2025-01-31 15:18:28 +13:00
.gitignore	pmgen: Move passes out of pmgen folder	2025-01-31 15:18:28 +13:00