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https://github.com/YosysHQ/yosys
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141 lines
2.7 KiB
Text
141 lines
2.7 KiB
Text
read_verilog -sv <<EOT
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module gold (input D, output Q);
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assign Q = '0;
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endmodule
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module gate (input D, output Q);
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assume property (D == '0);
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assign Q = D;
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endmodule
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EOT
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chformal -lower
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async2sync
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design -stash input
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# using $assert cells in sat verifies
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design -load input
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equiv_make -make_assert gold gate equiv
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prep -top equiv
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sat -set-assumes -prove-asserts -verify
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# this fails
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# sat -prove-asserts -verify
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# so should $equiv
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## in equiv_simple
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design -load input
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equiv_make gold gate equiv
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equiv_simple -set-assumes equiv
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equiv_status -assert equiv
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## and equiv_induct
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delete equiv
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equiv_make gold gate equiv
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equiv_induct -set-assumes equiv
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equiv_status -assert equiv
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# and it works through cells
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design -reset
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read_verilog -sv <<EOT
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module gold (input [1:0] D, output [1:0] Q);
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assign Q = !D;
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endmodule
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module gate (input [1:0] D, output [1:0] Q);
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assume property (D == 2'b11);
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wire [1:0] G = ~D;
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assign Q = G;
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endmodule
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EOT
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chformal -lower
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async2sync
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design -stash input2
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design -load input2
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equiv_make -make_assert gold gate equiv
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prep -top equiv
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sat -set-assumes -prove-asserts -verify
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design -load input2
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equiv_make gold gate equiv
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equiv_simple -set-assumes equiv
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equiv_status -assert equiv
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delete equiv
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equiv_make gold gate equiv
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equiv_induct -set-assumes equiv
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equiv_status -assert equiv
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# and registers
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design -reset
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read_verilog -sv <<EOT
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module gold (input clk, input [1:0] D, output [1:0] Q);
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assign Q = '0;
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endmodule
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module gate (input clk, input [1:0] D, output [1:0] Q);
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reg [1:0] Dreg;
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assume property (Dreg == 2'b11);
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always @(clk) begin
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Dreg <= D;
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end
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assign Q = ~Dreg;
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endmodule
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EOT
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proc
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chformal -lower
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async2sync
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design -stash input3
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design -load input3
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equiv_make -make_assert gold gate equiv
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prep -top equiv
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sat -set-assumes -prove-asserts -verify
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design -load input3
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equiv_make gold gate equiv
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equiv_simple -set-assumes equiv
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equiv_status -assert equiv
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delete equiv
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equiv_make gold gate equiv
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equiv_induct -set-assumes equiv
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equiv_status -assert equiv
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# so long as the assumption doesn't end up after the equiv
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design -reset
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read_verilog -sv <<EOT
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module gold (input [1:0] D, output [1:0] Q);
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assign Q = !D;
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endmodule
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module gate (input [1:0] D, output [1:0] Q);
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assume property (G == 2'b00);
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wire [1:0] G = ~D;
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assign Q = G;
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endmodule
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EOT
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chformal -lower
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async2sync
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design -stash input4
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logger -expect log "model found: FAIL!" 1
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logger -expect log "Found a total of 2 unproven .equiv cells." 2
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design -load input4
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equiv_make -make_assert gold gate equiv
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prep -top equiv
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sat -set-assumes -prove-asserts
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design -load input4
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equiv_make gold gate equiv
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equiv_simple -set-assumes equiv
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equiv_status equiv
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delete equiv
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equiv_make gold gate equiv
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equiv_induct -set-assumes equiv
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equiv_status equiv
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