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https://github.com/YosysHQ/yosys
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b1a8e73a60
- Fix explicit size cast of unbased unsized literals - Fix unbased unsized literal bound directly to port - Output `is_unsized` flag in `dumpAst`
8 lines
144 B
Plaintext
8 lines
144 B
Plaintext
read_verilog -sv unbased_unsized.sv
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hierarchy
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proc
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flatten
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opt -full
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select -module top
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sat -verify -seq 1 -tempinduct -prove-asserts -show-all
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