mirror of
https://github.com/YosysHQ/yosys
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122 lines
2.6 KiB
Text
122 lines
2.6 KiB
Text
read_verilog <<EOT
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module four_op_42(
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input [3:0] a, b, c, d,
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output [3:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -strategy 42
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design -load postopt
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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select -assert-count 2 t:$fa c:*emit_compressor_42* %i
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select -assert-count 0 t:$fa c:*emit_compressor_32* %i
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design -reset
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read_verilog <<EOT
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module four_op_fa(
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input [3:0] a, b, c, d,
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output [3:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -strategy fa
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design -load postopt
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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select -assert-count 0 t:$fa c:*emit_compressor_42* %i
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select -assert-count 2 t:$fa c:*emit_compressor_32* %i
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design -reset
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read_verilog <<EOT
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module eight_op_42(
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input [3:0] a, b, c, d, e, f, g, h,
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output [3:0] y
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);
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assign y = a + b + c + d + e + f + g + h;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -strategy 42
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design -load postopt
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select -assert-count 6 t:$fa
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select -assert-count 1 t:$add
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select -assert-min 1 t:$fa c:*emit_compressor_42* %i
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design -reset
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read_verilog <<EOT
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module sixteen_op_42(
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input [3:0] a0, a1, a2, a3, a4, a5, a6, a7,
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input [3:0] a8, a9, a10, a11, a12, a13, a14, a15,
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output [3:0] y
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);
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assign y = a0 + a1 + a2 + a3 + a4 + a5 + a6 + a7
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+ a8 + a9 + a10 + a11 + a12 + a13 + a14 + a15;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -strategy 42
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design -load postopt
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select -assert-count 14 t:$fa
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select -assert-count 1 t:$add
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select -assert-min 1 t:$fa c:*emit_compressor_42* %i
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design -reset
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read_verilog <<EOT
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module five_op_42(
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input [3:0] a, b, c, d, e,
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output [3:0] y
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);
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assign y = a + b + c + d + e;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -strategy 42
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design -load postopt
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select -assert-count 3 t:$fa
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select -assert-count 1 t:$add
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select -assert-min 1 t:$fa c:*emit_compressor_42* %i
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design -reset
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read_verilog <<EOT
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module six_op_42(
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input [3:0] a, b, c, d, e, f,
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output [3:0] y
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);
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assign y = a + b + c + d + e + f;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -strategy 42
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design -load postopt
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select -assert-count 4 t:$fa
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select -assert-count 1 t:$add
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select -assert-min 1 t:$fa c:*emit_compressor_42* %i
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design -reset
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read_verilog <<EOT
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module seven_op_42(
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input [3:0] a, b, c, d, e, f, g,
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output [3:0] y
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);
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assign y = a + b + c + d + e + f + g;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -strategy 42
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design -load postopt
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select -assert-count 5 t:$fa
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select -assert-count 1 t:$add
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select -assert-min 1 t:$fa c:*emit_compressor_42* %i
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design -reset
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