Sean Anderson 8c05f14b58 Order ports with default assignments first ... Although the current style is allowed by the standard, Icarus verilog doesn't parse default assignments using an implicit net type: techlibs/ice40/cells_sim.v:305: syntax error techlibs/ice40/cells_sim.v:1: Errors in port declarations. Fix this by making sure that ports with default assignments first on their line. Fixes: 46d3f03d2 ("Add default assignments to other SB_* simulation models") Signed-off-by: Sean Anderson <seanga2@gmail.com>		2022-08-09 23:42:24 -04:00
..
tests
abc9_model.v	Fix icestorm links	2021-06-09 12:39:12 +02:00
arith_map.v
brams.txt	ice40: Use memory_libmap pass.	2022-05-18 17:32:56 +02:00
brams_map.v	ice40: Use memory_libmap pass.	2022-05-18 17:32:56 +02:00
cells_map.v
cells_sim.v	Order ports with default assignments first	2022-08-09 23:42:24 -04:00
dsp_map.v
ff_map.v
ice40_braminit.cc
ice40_opt.cc
latches_map.v
Makefile.inc	ice40: Use memory_libmap pass.	2022-05-18 17:32:56 +02:00
spram.txt	ice40: Use memory_libmap pass.	2022-05-18 17:32:56 +02:00
spram_map.v	ice40: Use memory_libmap pass.	2022-05-18 17:32:56 +02:00
synth_ice40.cc	Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.	2022-06-02 23:16:12 +02:00