mirror of
https://github.com/YosysHQ/yosys
synced 2026-03-02 19:56:57 +00:00
19 lines
262 B
Systemverilog
19 lines
262 B
Systemverilog
module top (
|
|
input clk,
|
|
input a, b, c, d
|
|
);
|
|
default clocking @(posedge clk); endclocking
|
|
|
|
assert property (
|
|
a ##[*] b |=> c until ##[*] d
|
|
);
|
|
|
|
`ifndef FAIL
|
|
assume property (
|
|
b |=> ##5 d
|
|
);
|
|
assume property (
|
|
b || (c && !d) |=> c
|
|
);
|
|
`endif
|
|
endmodule
|