yosys/tests/verilog/.gitignore at b11cf67a8170ee830beedadc7156c4e83e4f1134 - mirrors/yosys - Libre-Chip.org

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Eddie Hung b11cf67a81 Setup tests/verilog properly

2020-05-11 10:31:02 -07:00

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	`/*.log`
	`/*.out`
	`/run-test.mk`