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7 lines
133 B
Verilog
7 lines
133 B
Verilog
module test(a, b, c, d, e, f, y);
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input [19:0] a, b, c;
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input [15:0] d, e, f;
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output [41:0] y;
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assign y = a*b + c*d + e*f;
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endmodule
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