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yosys/techlibs
clairexen e919d0c125
Merge pull request #2405 from byuccl/fix_xilinx_cells
xilinx/cells_sim.v: Move signal declaration to before first use
2020-10-20 17:11:36 +02:00
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achronix
anlogic
common Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixes 2020-08-20 16:25:56 +02:00
coolrunner2
easic
ecp5 Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
efinix techmap: Add support for [] wildcards in techmap_celltype. 2020-08-02 22:46:48 +02:00
gowin Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
greenpak4 opt_expr: Remove -clkinv option, make it the default. 2020-07-31 00:08:15 +02:00
ice40 Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
intel synth_intel: Remove incomplete Arria 10 GX support. 2020-08-21 01:46:06 +02:00
intel_alm intel_alm: better map wide but shallow multiplies 2020-08-28 23:44:16 +02:00
nexus synth_nexus: Initial implementation 2020-10-15 08:52:15 +01:00
sf2
xilinx Move signal declarations to before first use 2020-10-19 16:09:18 -06:00
.gitignore