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27 lines
1.2 KiB
Text
27 lines
1.2 KiB
Text
read_verilog ../common/counter.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_NOT
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select -assert-count 8 t:MISTRAL_ALUT_ARITH
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select -assert-count 8 t:MISTRAL_FF
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select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
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design -reset
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read_verilog ../common/counter.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_NOT
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select -assert-count 8 t:MISTRAL_ALUT_ARITH
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select -assert-count 8 t:MISTRAL_FF
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select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
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