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21 lines
464 B
Verilog
21 lines
464 B
Verilog
module example(CLK, LD);
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input CLK;
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output [15:0] LD;
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wire clock;
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reg [15:0] leds;
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BUFG CLK_BUF (.I(CLK), .O(clock));
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OBUF LD_BUF[15:0] (.I(leds), .O(LD));
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parameter COUNTBITS = 26;
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reg [COUNTBITS-1:0] counter;
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always @(posedge CLK) begin
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counter <= counter + 1;
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if (counter[COUNTBITS-1])
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leds <= 16'h8000 >> counter[COUNTBITS-2:COUNTBITS-5];
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else
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leds <= 16'h0001 << counter[COUNTBITS-2:COUNTBITS-5];
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end
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endmodule
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