Tony Min d41688f7d7 Revisions (#4) ... * area should be 1 for all LUTs * clean up macros * add log_assert to fail noisily when encountering oddly configured DFF * clean help msg * flatten set to true by default * update * merge mult tests * remove redundant test * move all dsp tests to single file and remove redundant tests * update ram tests * add more dff tests * fix c++20 compile errors * add option to dump verilog * default to use abc9 * remove -abc9 option since its the default now --------- Co-authored-by: tony <minchunlin@gmail.com>		2024-07-08 10:57:16 -04:00
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anlogic	Update tests	2023-06-09 14:41:45 +02:00
common	Adding double_sync_ram_tdp to blockram.v	2023-12-04 15:52:03 +01:00
ecp5	ice40, ecp5, gowin: enable ABC9 by default	2023-11-13 15:28:13 +00:00
efinix	efinix: Use memory_libmap pass.	2022-05-18 17:32:56 +02:00
fabulous	fabulous: Add support for mapping carry chains	2023-02-27 09:50:34 +01:00
gatemate	Update tests	2023-06-09 14:41:45 +02:00
gowin	ice40, ecp5, gowin: enable ABC9 by default	2023-11-13 15:28:13 +00:00
ice40	ice40, ecp5, gowin: enable ABC9 by default	2023-11-13 15:28:13 +00:00
intel_alm	intel_alm: drop quartus support	2024-05-03 11:32:33 +01:00
machxo2	put back previous test state, due to default change	2023-08-29 10:21:58 +02:00
microchip	Revisions (#4)	2024-07-08 10:57:16 -04:00
nexus	Update tests	2023-06-09 14:41:45 +02:00
quicklogic	Add workflows and CODEOWNERS and fixed gitignore	2024-04-11 14:56:00 +02:00
xilinx	tests: Run async2sync before sat and/or sim to handle $check cells	2024-02-01 16:14:11 +01:00
run-test.sh	Enable SV for localparam use by Efinix cell_sim	2024-04-08 12:45:43 +02:00