3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-03-01 19:26:55 +00:00
yosys/passes
2026-02-28 18:40:38 +01:00
..
cmds rtlil use newcelltypes. 2026-02-28 18:30:37 +01:00
equiv Merge branch 'main' into emil/turbo-celltypes 2026-02-28 18:40:38 +01:00
fsm fsm_detect: add adff detection 2025-11-06 23:29:47 +02:00
hierarchy hierarchy.cc: Tidying 2025-10-15 09:42:47 +13:00
memory memory_libmap: Add -force-params 2026-02-20 10:57:00 +00:00
opt Merge branch 'main' into emil/turbo-celltypes 2026-02-25 12:29:06 +01:00
pmgen Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
proc proc_clean: Removing an empty full_case is doing something 2026-01-07 13:10:32 +13:00
sat Merge branch 'main' into emil/turbo-celltypes 2026-02-28 18:40:38 +01:00
techmap Merge branch 'main' into emil/turbo-celltypes 2026-02-25 12:29:06 +01:00
tests test_cell.cc: Generate .aag for all compatible cells 2025-12-02 14:03:36 +13:00