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By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
32 lines
727 B
Verilog
32 lines
727 B
Verilog
module __MISTRAL_M10K_SDP(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 10;
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parameter CFG_DBITS = 10;
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parameter CFG_ENABLE_A = 1;
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parameter CFG_ENABLE_B = 1;
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input CLK1;
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input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
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input [CFG_DBITS-1:0] A1DATA;
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output [CFG_DBITS-1:0] B1DATA;
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input [CFG_ENABLE_A-1:0] A1EN, B1EN;
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altsyncram #(
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.operation_mode("dual_port"),
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.ram_block_type("m10k"),
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.widthad_a(CFG_ABITS),
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.width_a(CFG_DBITS),
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.widthad_b(CFG_ABITS),
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.width_b(CFG_DBITS),
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) _TECHMAP_REPLACE_ (
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.address_a(A1ADDR),
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.data_a(A1DATA),
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.wren_a(A1EN),
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.address_b(B1ADDR),
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.q_b(B1DATA),
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.clock0(CLK1),
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.clock1(CLK1)
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);
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endmodule
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