mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-20 14:20:32 +00:00
368 lines
9.3 KiB
C++
368 lines
9.3 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct ExclusiveDatabase
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{
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Module *module;
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const SigMap &sigmap;
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dict<SigBit, std::pair<SigSpec,std::vector<Const>>> sig_cmp_prev;
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ExclusiveDatabase(Module *module, const SigMap &sigmap) : module(module), sigmap(sigmap)
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{
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SigSpec const_sig, nonconst_sig;
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SigBit y_port;
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pool<Cell*> reduce_or;
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for (auto cell : module->cells()) {
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if (cell->type == ID($eq)) {
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nonconst_sig = sigmap(cell->getPort(ID::A));
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const_sig = sigmap(cell->getPort(ID::B));
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if (!const_sig.is_fully_const()) {
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if (!nonconst_sig.is_fully_const())
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continue;
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std::swap(nonconst_sig, const_sig);
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}
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y_port = sigmap(cell->getPort(ID::Y));
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}
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else if (cell->type == ID($logic_not)) {
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nonconst_sig = sigmap(cell->getPort(ID::A));
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const_sig = Const(State::S0, GetSize(nonconst_sig));
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y_port = sigmap(cell->getPort(ID::Y));
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}
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else if (cell->type == ID($reduce_or)) {
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reduce_or.insert(cell);
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continue;
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}
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else continue;
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log_assert(!nonconst_sig.empty());
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log_assert(!const_sig.empty());
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sig_cmp_prev[y_port] = std::make_pair(nonconst_sig,std::vector<Const>{const_sig.as_const()});
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}
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for (auto cell : reduce_or) {
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nonconst_sig = SigSpec();
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std::vector<Const> values;
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SigSpec a_port = sigmap(cell->getPort(ID::A));
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for (auto bit : a_port) {
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auto it = sig_cmp_prev.find(bit);
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if (it == sig_cmp_prev.end()) {
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nonconst_sig = SigSpec();
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break;
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}
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if (nonconst_sig.empty())
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nonconst_sig = it->second.first;
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else if (nonconst_sig != it->second.first) {
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nonconst_sig = SigSpec();
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break;
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}
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for (auto value : it->second.second)
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values.push_back(value);
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}
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if (nonconst_sig.empty())
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continue;
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y_port = sigmap(cell->getPort(ID::Y));
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sig_cmp_prev[y_port] = std::make_pair(nonconst_sig,std::move(values));
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}
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}
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bool query(const SigSpec &sig) const
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{
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SigSpec nonconst_sig;
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pool<Const> const_values;
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for (auto bit : sig) {
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auto it = sig_cmp_prev.find(bit);
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if (it == sig_cmp_prev.end())
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return false;
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if (nonconst_sig.empty())
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nonconst_sig = it->second.first;
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else if (nonconst_sig != it->second.first)
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return false;
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for (auto value : it->second.second)
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if (!const_values.insert(value).second)
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return false;
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}
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return true;
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}
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};
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struct MuxpackWorker
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{
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Module *module;
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SigMap sigmap;
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int mux_count, pmux_count;
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pool<Cell*> remove_cells;
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dict<SigSpec, Cell*> sig_chain_next;
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dict<SigSpec, Cell*> sig_chain_prev;
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pool<SigBit> sigbit_with_non_chain_users;
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pool<Cell*> chain_start_cells;
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pool<Cell*> candidate_cells;
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ExclusiveDatabase excl_db;
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void make_sig_chain_next_prev()
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{
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for (auto wire : module->wires())
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{
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if (wire->port_output || wire->get_bool_attribute(ID::keep)) {
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for (auto bit : sigmap(wire))
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sigbit_with_non_chain_users.insert(bit);
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}
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}
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for (auto cell : module->cells())
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{
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if (cell->type.in(ID($mux), ID($pmux)) && !cell->get_bool_attribute(ID::keep))
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{
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SigSpec a_sig = sigmap(cell->getPort(ID::A));
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SigSpec b_sig;
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if (cell->type == ID($mux))
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b_sig = sigmap(cell->getPort(ID::B));
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SigSpec y_sig = sigmap(cell->getPort(ID::Y));
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if (sig_chain_next.count(a_sig))
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for (auto a_bit : a_sig)
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sigbit_with_non_chain_users.insert(a_bit);
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else {
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sig_chain_next[a_sig] = cell;
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candidate_cells.insert(cell);
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}
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if (!b_sig.empty()) {
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if (sig_chain_next.count(b_sig))
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for (auto b_bit : b_sig)
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sigbit_with_non_chain_users.insert(b_bit);
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else {
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sig_chain_next[b_sig] = cell;
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candidate_cells.insert(cell);
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}
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}
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sig_chain_prev[y_sig] = cell;
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continue;
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}
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for (auto conn : cell->connections())
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if (cell->input(conn.first))
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for (auto bit : sigmap(conn.second))
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sigbit_with_non_chain_users.insert(bit);
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}
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}
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void find_chain_start_cells()
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{
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for (auto cell : candidate_cells)
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{
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log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type));
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SigSpec a_sig = sigmap(cell->getPort(ID::A));
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if (cell->type == ID($mux)) {
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SigSpec b_sig = sigmap(cell->getPort(ID::B));
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if (sig_chain_prev.count(a_sig) + sig_chain_prev.count(b_sig) != 1)
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goto start_cell;
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if (!sig_chain_prev.count(a_sig))
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a_sig = b_sig;
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}
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else if (cell->type == ID($pmux)) {
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if (!sig_chain_prev.count(a_sig))
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goto start_cell;
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}
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else log_abort();
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for (auto bit : a_sig)
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if (sigbit_with_non_chain_users.count(bit))
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goto start_cell;
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{
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Cell *prev_cell = sig_chain_prev.at(a_sig);
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log_assert(prev_cell);
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SigSpec s_sig = sigmap(cell->getPort(ID::S));
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s_sig.append(sigmap(prev_cell->getPort(ID::S)));
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if (!excl_db.query(s_sig))
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goto start_cell;
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}
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continue;
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start_cell:
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chain_start_cells.insert(cell);
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}
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}
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vector<Cell*> create_chain(Cell *start_cell)
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{
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vector<Cell*> chain;
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Cell *c = start_cell;
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while (c != nullptr)
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{
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chain.push_back(c);
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SigSpec y_sig = sigmap(c->getPort(ID::Y));
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if (sig_chain_next.count(y_sig) == 0)
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break;
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c = sig_chain_next.at(y_sig);
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if (chain_start_cells.count(c) != 0)
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break;
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}
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return chain;
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}
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void process_chain(vector<Cell*> &chain)
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{
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if (GetSize(chain) < 2)
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return;
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int cursor = 0;
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while (cursor < GetSize(chain))
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{
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int cases = GetSize(chain) - cursor;
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Cell *first_cell = chain[cursor];
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dict<int, SigBit> taps_dict;
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if (cases < 2) {
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cursor++;
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continue;
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}
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Cell *last_cell = chain[cursor+cases-1];
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log("Converting %s.%s ... %s.%s to a pmux with %d cases.\n",
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log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), cases);
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mux_count += cases;
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pmux_count += 1;
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first_cell->type = ID($pmux);
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SigSpec b_sig = first_cell->getPort(ID::B);
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SigSpec s_sig = first_cell->getPort(ID::S);
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for (int i = 1; i < cases; i++) {
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Cell* prev_cell = chain[cursor+i-1];
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Cell* cursor_cell = chain[cursor+i];
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if (sigmap(prev_cell->getPort(ID::Y)) == sigmap(cursor_cell->getPort(ID::A))) {
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b_sig.append(cursor_cell->getPort(ID::B));
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s_sig.append(cursor_cell->getPort(ID::S));
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}
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else {
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log_assert(cursor_cell->type == ID($mux));
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b_sig.append(cursor_cell->getPort(ID::A));
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s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID::S)));
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}
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remove_cells.insert(cursor_cell);
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}
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first_cell->setPort(ID::B, b_sig);
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first_cell->setPort(ID::S, s_sig);
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first_cell->setParam(ID::S_WIDTH, GetSize(s_sig));
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first_cell->setPort(ID::Y, last_cell->getPort(ID::Y));
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cursor += cases;
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}
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}
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void cleanup()
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{
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for (auto cell : remove_cells)
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module->remove(cell);
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remove_cells.clear();
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sig_chain_next.clear();
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sig_chain_prev.clear();
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chain_start_cells.clear();
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candidate_cells.clear();
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}
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MuxpackWorker(Module *module) :
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module(module), sigmap(module), mux_count(0), pmux_count(0), excl_db(module, sigmap)
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{
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make_sig_chain_next_prev();
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find_chain_start_cells();
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for (auto c : chain_start_cells) {
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vector<Cell*> chain = create_chain(c);
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process_chain(chain);
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}
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cleanup();
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}
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};
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struct MuxpackPass : public Pass {
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MuxpackPass() : Pass("muxpack", "$mux/$pmux cascades to $pmux") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" muxpack [selection]\n");
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log("\n");
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log("This pass converts cascaded chains of $pmux cells (e.g. those create from case\n");
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log("constructs) and $mux cells (e.g. those created by if-else constructs) into\n");
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log("$pmux cells.\n");
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log("\n");
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log("This optimisation is conservative --- it will only pack $mux or $pmux cells\n");
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log("whose select lines are driven by '$eq' cells with other such cells if it can be\n");
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log("certain that their select inputs are mutually exclusive.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing MUXPACK pass ($mux cell cascades to $pmux).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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break;
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}
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extra_args(args, argidx, design);
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int mux_count = 0;
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int pmux_count = 0;
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for (auto module : design->selected_modules()) {
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MuxpackWorker worker(module);
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mux_count += worker.mux_count;
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pmux_count += worker.pmux_count;
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}
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log("Converted %d (p)mux cells into %d pmux cells.\n", mux_count, pmux_count);
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}
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} MuxpackPass;
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PRIVATE_NAMESPACE_END
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