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https://github.com/YosysHQ/yosys
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344 lines
10 KiB
Verilog
344 lines
10 KiB
Verilog
// Copyright 2020-2022 F4PGA Authors
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype wire
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module TDP18K_FIFO (
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RMODE_A_i,
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RMODE_B_i,
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WMODE_A_i,
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WMODE_B_i,
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WEN_A_i,
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WEN_B_i,
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REN_A_i,
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REN_B_i,
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CLK_A_i,
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CLK_B_i,
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BE_A_i,
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BE_B_i,
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ADDR_A_i,
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ADDR_B_i,
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WDATA_A_i,
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WDATA_B_i,
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RDATA_A_o,
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RDATA_B_o,
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EMPTY_o,
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EPO_o,
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EWM_o,
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UNDERRUN_o,
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FULL_o,
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FMO_o,
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FWM_o,
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OVERRUN_o,
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FLUSH_ni,
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FMODE_i,
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);
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parameter SYNC_FIFO_i = 1'b0;
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parameter POWERDN_i = 1'b0;
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parameter SLEEP_i = 1'b0;
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parameter PROTECT_i = 1'b0;
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parameter UPAF_i = 11'b0;
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parameter UPAE_i = 11'b0;
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parameter [18*1024-1:0] INIT_i = 18431'bx;
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input wire [2:0] RMODE_A_i;
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input wire [2:0] RMODE_B_i;
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input wire [2:0] WMODE_A_i;
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input wire [2:0] WMODE_B_i;
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input wire WEN_A_i;
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input wire WEN_B_i;
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input wire REN_A_i;
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input wire REN_B_i;
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(* clkbuf_sink *)
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input wire CLK_A_i;
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(* clkbuf_sink *)
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input wire CLK_B_i;
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input wire [1:0] BE_A_i;
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input wire [1:0] BE_B_i;
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input wire [13:0] ADDR_A_i;
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input wire [13:0] ADDR_B_i;
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input wire [17:0] WDATA_A_i;
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input wire [17:0] WDATA_B_i;
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output reg [17:0] RDATA_A_o;
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output reg [17:0] RDATA_B_o;
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output wire EMPTY_o;
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output wire EPO_o;
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output wire EWM_o;
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output wire UNDERRUN_o;
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output wire FULL_o;
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output wire FMO_o;
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output wire FWM_o;
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output wire OVERRUN_o;
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input wire FLUSH_ni;
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input wire FMODE_i;
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reg [17:0] wmsk_a;
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reg [17:0] wmsk_b;
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wire [8:0] addr_a;
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wire [8:0] addr_b;
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reg [4:0] addr_a_d;
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reg [4:0] addr_b_d;
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wire [17:0] ram_rdata_a;
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wire [17:0] ram_rdata_b;
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reg [17:0] aligned_wdata_a;
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reg [17:0] aligned_wdata_b;
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wire ren_o;
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wire [10:0] ff_raddr;
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wire [10:0] ff_waddr;
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wire [13:0] ram_addr_a;
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wire [13:0] ram_addr_b;
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wire [3:0] ram_waddr_a;
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wire [3:0] ram_waddr_b;
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wire initn;
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wire smux_rclk;
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wire smux_wclk;
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wire real_fmode;
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wire [3:0] raw_fflags;
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reg [1:0] fifo_rmode;
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reg [1:0] fifo_wmode;
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wire smux_clk_a;
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wire smux_clk_b;
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wire ram_ren_a;
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wire ram_ren_b;
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wire ram_wen_a;
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wire ram_wen_b;
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wire cen_a;
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wire cen_b;
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wire cen_a_n;
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wire cen_b_n;
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wire ram_wen_a_n;
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wire ram_wen_b_n;
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localparam MODE_9 = 3'b001;
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always @(*) begin
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fifo_rmode = (RMODE_B_i == MODE_9 ? 2'b10 : 2'b01);
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fifo_wmode = (WMODE_A_i == MODE_9 ? 2'b10 : 2'b01);
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end
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assign smux_clk_a = CLK_A_i;
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assign smux_clk_b = CLK_B_i;
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assign real_fmode = FMODE_i;
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assign ram_ren_b = real_fmode ? ren_o : REN_B_i;
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assign ram_wen_a = FMODE_i ? ~FULL_o & WEN_A_i : WEN_A_i;
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assign ram_ren_a = FMODE_i ? 0 : REN_A_i;
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assign ram_wen_b = FMODE_i ? 1'b0 : WEN_B_i;
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assign cen_b = ram_ren_b | ram_wen_b;
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assign cen_a = ram_ren_a | ram_wen_a;
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assign ram_waddr_b = real_fmode ? {ff_raddr[0], 3'b000} : ADDR_B_i[3:0];
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assign ram_waddr_a = real_fmode ? {ff_waddr[0], 3'b000} : ADDR_A_i[3:0];
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assign ram_addr_b = real_fmode ? {ff_raddr[10:0], 3'h0} : {ADDR_B_i[13:4], addr_b_d[3:0]};
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assign ram_addr_a = real_fmode ? {ff_waddr[10:0], 3'h0} : {ADDR_A_i[13:4], addr_a_d[3:0]};
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always @(posedge CLK_A_i) addr_a_d[3:0] <= ADDR_A_i[3:0];
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always @(posedge CLK_B_i) addr_b_d[3:0] <= ADDR_B_i[3:0];
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assign cen_a_n = ~cen_a;
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assign ram_wen_a_n = ~ram_wen_a;
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assign cen_b_n = ~cen_b;
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assign ram_wen_b_n = ~ram_wen_b;
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sram1024x18 #(
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.init(INIT_i)
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) uram(
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.clk_a(smux_clk_a),
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.cen_a(cen_a_n),
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.wen_a(ram_wen_a_n),
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.addr_a(ram_addr_a[13:4]),
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.wmsk_a(wmsk_a),
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.wdata_a(aligned_wdata_a),
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.rdata_a(ram_rdata_a),
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.clk_b(smux_clk_b),
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.cen_b(cen_b_n),
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.wen_b(ram_wen_b_n),
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.addr_b(ram_addr_b[13:4]),
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.wmsk_b(wmsk_b),
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.wdata_b(aligned_wdata_b),
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.rdata_b(ram_rdata_b)
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);
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fifo_ctl #(
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.ADDR_WIDTH(11),
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.FIFO_WIDTH(2),
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.DEPTH(6)
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) fifo_ctl(
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.rclk(smux_clk_b),
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.rst_R_n(FLUSH_ni),
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.wclk(smux_clk_a),
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.rst_W_n(FLUSH_ni),
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.ren(REN_B_i),
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.wen(ram_wen_a),
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.sync(SYNC_FIFO_i),
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.rmode(fifo_rmode),
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.wmode(fifo_wmode),
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.ren_o(ren_o),
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.fflags({FULL_o, FMO_o, FWM_o, OVERRUN_o, EMPTY_o, EPO_o, EWM_o, UNDERRUN_o}),
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.raddr(ff_raddr),
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.waddr(ff_waddr),
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.upaf(UPAF_i),
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.upae(UPAE_i)
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);
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localparam MODE_1 = 3'b101;
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localparam MODE_18 = 3'b010;
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localparam MODE_2 = 3'b110;
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localparam MODE_4 = 3'b100;
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always @(*) begin : WDATA_MODE_SEL
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if (ram_wen_a == 1) begin
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case (WMODE_A_i)
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MODE_18: begin
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aligned_wdata_a = WDATA_A_i;
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{wmsk_a[17], wmsk_a[15:8]} = (FMODE_i ? 9'h000 : (BE_A_i[1] ? 9'h000 : 9'h1ff));
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{wmsk_a[16], wmsk_a[7:0]} = (FMODE_i ? 9'h000 : (BE_A_i[0] ? 9'h000 : 9'h1ff));
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end
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MODE_9: begin
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aligned_wdata_a = {{2 {WDATA_A_i[16]}}, {2 {WDATA_A_i[7:0]}}};
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{wmsk_a[17], wmsk_a[15:8]} = (ram_waddr_a[3] ? 9'h000 : 9'h1ff);
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{wmsk_a[16], wmsk_a[7:0]} = (ram_waddr_a[3] ? 9'h1ff : 9'h000);
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end
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MODE_4: begin
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aligned_wdata_a = {2'b00, {4 {WDATA_A_i[3:0]}}};
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wmsk_a[17:16] = 2'b00;
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wmsk_a[15:12] = (ram_waddr_a[3:2] == 2'b11 ? 4'h0 : 4'hf);
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wmsk_a[11:8] = (ram_waddr_a[3:2] == 2'b10 ? 4'h0 : 4'hf);
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wmsk_a[7:4] = (ram_waddr_a[3:2] == 2'b01 ? 4'h0 : 4'hf);
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wmsk_a[3:0] = (ram_waddr_a[3:2] == 2'b00 ? 4'h0 : 4'hf);
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end
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MODE_2: begin
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aligned_wdata_a = {2'b00, {8 {WDATA_A_i[1:0]}}};
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wmsk_a[17:16] = 2'b00;
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wmsk_a[15:14] = (ram_waddr_a[3:1] == 3'b111 ? 2'h0 : 2'h3);
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wmsk_a[13:12] = (ram_waddr_a[3:1] == 3'b110 ? 2'h0 : 2'h3);
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wmsk_a[11:10] = (ram_waddr_a[3:1] == 3'b101 ? 2'h0 : 2'h3);
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wmsk_a[9:8] = (ram_waddr_a[3:1] == 3'b100 ? 2'h0 : 2'h3);
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wmsk_a[7:6] = (ram_waddr_a[3:1] == 3'b011 ? 2'h0 : 2'h3);
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wmsk_a[5:4] = (ram_waddr_a[3:1] == 3'b010 ? 2'h0 : 2'h3);
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wmsk_a[3:2] = (ram_waddr_a[3:1] == 3'b001 ? 2'h0 : 2'h3);
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wmsk_a[1:0] = (ram_waddr_a[3:1] == 3'b000 ? 2'h0 : 2'h3);
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end
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MODE_1: begin
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aligned_wdata_a = {2'b00, {16 {WDATA_A_i[0]}}};
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wmsk_a = 18'h0ffff;
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wmsk_a[{1'b0, ram_waddr_a[3:0]}] = 0;
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end
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default: wmsk_a = 18'h3ffff;
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endcase
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end
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else begin
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aligned_wdata_a = 18'h00000;
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wmsk_a = 18'h3ffff;
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end
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if (ram_wen_b == 1)
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case (WMODE_B_i)
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MODE_18: begin
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aligned_wdata_b = WDATA_B_i;
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{wmsk_b[17], wmsk_b[15:8]} = (BE_B_i[1] ? 9'h000 : 9'h1ff);
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{wmsk_b[16], wmsk_b[7:0]} = (BE_B_i[0] ? 9'h000 : 9'h1ff);
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end
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MODE_9: begin
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aligned_wdata_b = {{2 {WDATA_B_i[16]}}, {2 {WDATA_B_i[7:0]}}};
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{wmsk_b[17], wmsk_b[15:8]} = (ram_waddr_b[3] ? 9'h000 : 9'h1ff);
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{wmsk_b[16], wmsk_b[7:0]} = (ram_waddr_b[3] ? 9'h1ff : 9'h000);
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end
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MODE_4: begin
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aligned_wdata_b = {2'b00, {4 {WDATA_B_i[3:0]}}};
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wmsk_b[17:16] = 2'b00;
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wmsk_b[15:12] = (ram_waddr_b[3:2] == 2'b11 ? 4'h0 : 4'hf);
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wmsk_b[11:8] = (ram_waddr_b[3:2] == 2'b10 ? 4'h0 : 4'hf);
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wmsk_b[7:4] = (ram_waddr_b[3:2] == 2'b01 ? 4'h0 : 4'hf);
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wmsk_b[3:0] = (ram_waddr_b[3:2] == 2'b00 ? 4'h0 : 4'hf);
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end
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MODE_2: begin
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aligned_wdata_b = {2'b00, {8 {WDATA_B_i[1:0]}}};
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wmsk_b[17:16] = 2'b00;
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wmsk_b[15:14] = (ram_waddr_b[3:1] == 3'b111 ? 2'h0 : 2'h3);
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wmsk_b[13:12] = (ram_waddr_b[3:1] == 3'b110 ? 2'h0 : 2'h3);
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wmsk_b[11:10] = (ram_waddr_b[3:1] == 3'b101 ? 2'h0 : 2'h3);
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wmsk_b[9:8] = (ram_waddr_b[3:1] == 3'b100 ? 2'h0 : 2'h3);
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wmsk_b[7:6] = (ram_waddr_b[3:1] == 3'b011 ? 2'h0 : 2'h3);
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wmsk_b[5:4] = (ram_waddr_b[3:1] == 3'b010 ? 2'h0 : 2'h3);
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wmsk_b[3:2] = (ram_waddr_b[3:1] == 3'b001 ? 2'h0 : 2'h3);
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wmsk_b[1:0] = (ram_waddr_b[3:1] == 3'b000 ? 2'h0 : 2'h3);
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end
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MODE_1: begin
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aligned_wdata_b = {2'b00, {16 {WDATA_B_i[0]}}};
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wmsk_b = 18'h0ffff;
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wmsk_b[{1'b0, ram_waddr_b[3:0]}] = 0;
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end
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default: wmsk_b = 18'h3ffff;
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endcase
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else begin
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aligned_wdata_b = 18'b000000000000000000;
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wmsk_b = 18'h3ffff;
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end
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end
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always @(*) begin : RDATA_A_MODE_SEL
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case (RMODE_A_i)
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default: RDATA_A_o = 18'h00000;
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MODE_18: RDATA_A_o = ram_rdata_a;
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MODE_9: begin
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{RDATA_A_o[17], RDATA_A_o[15:8]} = 9'h000;
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{RDATA_A_o[16], RDATA_A_o[7:0]} = (ram_addr_a[3] ? {ram_rdata_a[17], ram_rdata_a[15:8]} : {ram_rdata_a[16], ram_rdata_a[7:0]});
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end
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MODE_4: begin
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RDATA_A_o[17:4] = 14'h0000;
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case (ram_addr_a[3:2])
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3: RDATA_A_o[3:0] = ram_rdata_a[15:12];
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2: RDATA_A_o[3:0] = ram_rdata_a[11:8];
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1: RDATA_A_o[3:0] = ram_rdata_a[7:4];
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0: RDATA_A_o[3:0] = ram_rdata_a[3:0];
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endcase
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end
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MODE_2: begin
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RDATA_A_o[17:2] = 16'h0000;
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case (ram_addr_a[3:1])
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7: RDATA_A_o[1:0] = ram_rdata_a[15:14];
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6: RDATA_A_o[1:0] = ram_rdata_a[13:12];
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5: RDATA_A_o[1:0] = ram_rdata_a[11:10];
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4: RDATA_A_o[1:0] = ram_rdata_a[9:8];
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3: RDATA_A_o[1:0] = ram_rdata_a[7:6];
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2: RDATA_A_o[1:0] = ram_rdata_a[5:4];
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1: RDATA_A_o[1:0] = ram_rdata_a[3:2];
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0: RDATA_A_o[1:0] = ram_rdata_a[1:0];
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endcase
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end
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MODE_1: begin
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RDATA_A_o[17:1] = 17'h00000;
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RDATA_A_o[0] = ram_rdata_a[ram_addr_a[3:0]];
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end
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endcase
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end
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always @(*)
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case (RMODE_B_i)
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default: RDATA_B_o = 18'h15566;
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MODE_18: RDATA_B_o = ram_rdata_b;
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MODE_9: begin
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{RDATA_B_o[17], RDATA_B_o[15:8]} = 9'b000000000;
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{RDATA_B_o[16], RDATA_B_o[7:0]} = (ram_addr_b[3] ? {ram_rdata_b[17], ram_rdata_b[15:8]} : {ram_rdata_b[16], ram_rdata_b[7:0]});
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end
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MODE_4:
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case (ram_addr_b[3:2])
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3: RDATA_B_o[3:0] = ram_rdata_b[15:12];
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2: RDATA_B_o[3:0] = ram_rdata_b[11:8];
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1: RDATA_B_o[3:0] = ram_rdata_b[7:4];
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0: RDATA_B_o[3:0] = ram_rdata_b[3:0];
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endcase
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MODE_2:
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case (ram_addr_b[3:1])
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7: RDATA_B_o[1:0] = ram_rdata_b[15:14];
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6: RDATA_B_o[1:0] = ram_rdata_b[13:12];
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5: RDATA_B_o[1:0] = ram_rdata_b[11:10];
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4: RDATA_B_o[1:0] = ram_rdata_b[9:8];
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3: RDATA_B_o[1:0] = ram_rdata_b[7:6];
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2: RDATA_B_o[1:0] = ram_rdata_b[5:4];
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1: RDATA_B_o[1:0] = ram_rdata_b[3:2];
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0: RDATA_B_o[1:0] = ram_rdata_b[1:0];
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endcase
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MODE_1: RDATA_B_o[0] = ram_rdata_b[{1'b0, ram_addr_b[3:0]}];
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endcase
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endmodule
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`default_nettype none
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