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yosys/techlibs/intel/arria10gx
2020-05-19 01:42:40 +02:00
..
cells_arith.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
cells_map.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
cells_sim.v synth_intel: a10gx -> arria10gx 2019-12-10 13:48:10 +00:00