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s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
73 lines
2.6 KiB
Verilog
73 lines
2.6 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
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// > Achronix eFPGA technology mapping. User must first simulate the generated \
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// > netlist before going to test it on board/custom chip.
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// > Input/Output buffers <
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// Input buffer map
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module \$__inpad (input I, output O);
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PADIN _TECHMAP_REPLACE_ (.padout(O), .padin(I));
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endmodule
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// Output buffer map
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module \$__outpad (input I, output O);
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PADOUT _TECHMAP_REPLACE_ (.padout(O), .padin(I), .oe(1'b1));
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endmodule
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// > end buffers <
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// > Look-Up table <
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// > VT: I still think Achronix folks would have chosen a better \
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// > logic architecture.
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// LUT Map
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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(* force_downto *)
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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// VT: This is not consistent and ACE will complain: assign Y = ~A[0];
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LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
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(.dout(Y), .din0(A[0]), .din1(1'b0), .din2(1'b0), .din3(1'b0));
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end else
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if (WIDTH == 2) begin
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LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
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(.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0), .din3(1'b0));
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end else
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if(WIDTH == 3) begin
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LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_
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(.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(1'b0));
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end else
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if(WIDTH == 4) begin
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LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_
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(.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
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end else
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wire _TECHMAP_FAIL_ = 1;
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endgenerate
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endmodule
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// > end LUT <
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// > Flops <
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// DFF flop
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module \$_DFF_P_ (input D, C, output Q);
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DFF _TECHMAP_REPLACE_
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(.q(Q), .d(D), .ck(C));
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endmodule
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