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yosys/techlibs/common
2020-05-05 08:01:27 -07:00
..
.gitignore
abc9_model.v Create +/abc9_model.v for $__ABC9_{DELAY,FF_} 2020-02-27 10:17:29 -08:00
adff2dff.v
cellhelp.py Progress on cell help messages 2015-10-17 02:35:19 +02:00
cells.lib
cmp2lcu.v techlibs/common: more robustness when *_WIDTH = 0 2020-05-05 08:01:27 -07:00
cmp2lut.v Cleanup +/cmp2lut.v 2020-04-03 14:28:22 -07:00
dff2ff.v Add dff2ff.v techmap file 2017-05-31 11:45:58 +02:00
gate2lut.v Fix invalid verilog syntax 2020-03-14 14:33:44 +01:00
gen_fine_ffs.py Fix the truth table for $_SR_* cells. 2020-04-15 17:17:48 +02:00
Makefile.inc techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu 2020-04-03 14:28:22 -07:00
mul2dsp.v Missing (* mul2dsp *) for sliceB 2019-09-27 14:21:47 -07:00
pmux2mux.v
prep.cc Add "wreduce -keepdc", fixes #1016 2019-05-20 15:36:13 +02:00
simcells.v Fix the truth table for $_SR_* cells. 2020-04-15 17:17:48 +02:00
simlib.v Fix the truth table for $_SR_* cells. 2020-04-15 17:17:48 +02:00
synth.cc synth: only techmap cmp2{lut,lcu} if -lut 2020-04-03 14:28:22 -07:00
techmap.v techlibs/common: more robustness when *_WIDTH = 0 2020-05-05 08:01:27 -07:00