mirror of
https://github.com/YosysHQ/yosys
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bc66dfd9ea
The following SV module at HEAD imported with verific,
```systemverilog
module my_module(
input logic [4:0] a,
input logic clk,
input logic enable,
output logic [4:0] z
);
reg [4:0] pipeline_register;
always @(posedge clk) begin
pipeline_register <= enable ? a : pipeline_register;
end
assign z = pipeline_register;
endmodule : my_module
```
results in the following output verilog
```systemverilog
/* Generated by 0.36 */
(* top = 1 *)
(* hdlname = "my_module" *)
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:2.12-2.21" *)
module my_module(clk, enable, a, z);
wire [4:0] _0_;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:3.25-3.26" *)
input [4:0] a;
wire [4:0] a;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:4.19-4.22" *)
input clk;
wire clk;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:5.19-5.25" *)
input enable;
wire enable;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:6.26-6.27" *)
output [4:0] z;
wire [4:0] z;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:10.12-12.8" *)
\$aldff #(
.ALOAD_POLARITY(32'd1),
.CLK_POLARITY(32'd1),
.WIDTH(32'd5)
) _1_ (
.AD(5'hxx),
.ALOAD(1'h0),
.CLK(clk),
.D(_0_),
.Q(z)
);
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:11.28-11.58" *)
\$mux #(
.WIDTH(32'd5)
) _2_ (
.A(z),
.B(a),
.S(enable),
.Y(_0_)
);
endmodule
```
Yosys is incorrectly infering aldffs due to an incorrect conversion
of logical 1 and 0 SigBits.
My PR unifies the conversion of Verific::Net objects into SigBits using
Yosys' internal representation of special signals like 0,1,x,z. After
my PR these signals are correctly converted into DFFs.
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
114 lines
4.5 KiB
C++
114 lines
4.5 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifdef YOSYS_ENABLE_VERIFIC
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#include "DataBase.h"
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YOSYS_NAMESPACE_BEGIN
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extern int verific_verbose;
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extern bool verific_import_pending;
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extern std::string verific_import(Design *design, const std::map<std::string,std::string> ¶meters, std::string top = std::string());
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extern pool<int> verific_sva_prims;
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struct VerificImporter;
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struct VerificClocking {
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RTLIL::Module *module = nullptr;
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Verific::Net *clock_net = nullptr;
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Verific::Net *enable_net = nullptr;
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Verific::Net *disable_net = nullptr;
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Verific::Net *body_net = nullptr;
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Verific::Net *cond_net = nullptr;
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SigBit clock_sig = State::Sx;
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SigBit enable_sig = State::S1;
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SigBit disable_sig = State::S0;
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bool posedge = true;
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bool gclk = false;
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bool cond_pol = true;
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VerificClocking() { }
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VerificClocking(VerificImporter *importer, Verific::Net *net, bool sva_at_only = false);
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RTLIL::Cell *addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const init_value = Const());
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RTLIL::Cell *addAdff(IdString name, RTLIL::SigSpec sig_arst, SigSpec sig_d, SigSpec sig_q, Const arst_value);
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RTLIL::Cell *addDffsr(IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, SigSpec sig_d, SigSpec sig_q);
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RTLIL::Cell *addAldff(IdString name, RTLIL::SigSpec sig_aload, RTLIL::SigSpec sig_adata, SigSpec sig_d, SigSpec sig_q);
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bool property_matches_sequence(const VerificClocking &seq) const {
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if (clock_net != seq.clock_net)
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return false;
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if (enable_net != seq.enable_net)
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return false;
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if (posedge != seq.posedge)
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return false;
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return true;
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}
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};
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struct VerificImporter
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{
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RTLIL::Module *module;
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Verific::Netlist *netlist;
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std::map<Verific::Net*, RTLIL::SigBit> net_map;
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std::map<Verific::Net*, Verific::Net*> sva_posedge_map;
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pool<Verific::Net*, hash_ptr_ops> any_all_nets;
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bool mode_gates, mode_keep, mode_nosva, mode_names, mode_verific;
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bool mode_autocover, mode_fullinit;
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VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_names, bool mode_verific, bool mode_autocover, bool mode_fullinit);
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RTLIL::SigBit net_map_at(Verific::Net *net);
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RTLIL::IdString new_verific_id(Verific::DesignObj *obj);
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void import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, Verific::DesignObj *obj, Verific::Netlist *nl = nullptr);
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RTLIL::SigBit netToSigBit(Verific::Net *net);
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RTLIL::SigSpec operatorInput(Verific::Instance *inst);
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RTLIL::SigSpec operatorInput1(Verific::Instance *inst);
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RTLIL::SigSpec operatorInput2(Verific::Instance *inst);
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RTLIL::SigSpec operatorInport(Verific::Instance *inst, const char *portname);
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RTLIL::SigSpec operatorInportCase(Verific::Instance *inst, const char *portname);
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RTLIL::SigSpec operatorOutput(Verific::Instance *inst, const pool<Verific::Net*, hash_ptr_ops> *any_all_nets = nullptr);
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bool import_netlist_instance_gates(Verific::Instance *inst, RTLIL::IdString inst_name);
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bool import_netlist_instance_cells(Verific::Instance *inst, RTLIL::IdString inst_name);
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void merge_past_ffs_clock(pool<RTLIL::Cell*> &candidates, SigBit clock, bool clock_pol);
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void merge_past_ffs(pool<RTLIL::Cell*> &candidates);
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void import_netlist(RTLIL::Design *design, Verific::Netlist *nl, std::map<std::string,Verific::Netlist*> &nl_todo, bool norename = false);
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};
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void verific_import_sva_assert(VerificImporter *importer, Verific::Instance *inst);
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void verific_import_sva_assume(VerificImporter *importer, Verific::Instance *inst);
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void verific_import_sva_cover(VerificImporter *importer, Verific::Instance *inst);
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void verific_import_sva_trigger(VerificImporter *importer, Verific::Instance *inst);
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bool verific_is_sva_net(VerificImporter *importer, Verific::Net *net);
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extern int verific_sva_fsm_limit;
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YOSYS_NAMESPACE_END
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#endif
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