yosys/tests/various/const_arg_loop.ys at ad2960adb7ae66d524e4ac5f8f5c16cbca3730e2 - mirrors/yosys - Libre-Chip.org

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Zachary Snow b6af90fe20 verilog: fix sizing of constant args for tasks/functions

- Simplify synthetic localparams for normal calls to update their width
    - This step was inadvertently removed alongside `added_mod_children`
- Support redeclaration of constant function arguments
    - `eval_const_function` never correctly handled this, but the issue
      was not exposed in the existing tests until the recent change to
      always attempt constant function evaluation when all-const args
      are used
- Check asserts in const_arg_loop and const_func tests
- Add coverage for width mismatch error cases

2021-02-21 15:44:43 -05:00

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 read_verilog -sv const_arg_loop.sv
 hierarchy
 proc
 opt -full
 select -module top
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all