3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-08-01 03:44:05 +00:00
yosys/backends
2020-04-04 22:13:25 +00:00
..
aiger xaiger: remove some unnecessary operations ... 2020-03-06 10:51:47 -08:00
blif
btor Use cell name for btor bad state props when it is a public name 2019-11-14 11:57:38 +01:00
edif edif: more resilience to mismatched port connection sizes. 2020-02-06 18:45:03 +01:00
firrtl remove include where not used 2020-03-13 14:55:53 +01:00
ilang
intersynth
json json: Change compat mode to directly emit ints <= 32 bits 2020-02-09 01:01:18 -08:00
protobuf Add aiger and protobuf backends binary support 2019-09-28 09:51:48 +02:00
simplec
smt2 Updated yosys-smtbmc to optionally dump raw bit strings, and fixed hole value recovery using that mode. 2020-04-04 22:13:25 +00:00
smv
spice
table
verilog specify: system timing checks to accept min:typ:max triple 2020-02-13 12:42:15 -08:00