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yosys/frontends/verilog
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Udi Finkelstein ac10e7d96d Initial implementation of elaboration system tasks 
(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.
2019-05-03 03:10:43 +03:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
const2ast.cc Convert more log_error() to log_file_error() where possible. 2018-07-20 09:37:44 -07:00
Makefile.inc Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906 2019-03-29 16:32:44 +01:00
preproc.cc Support SystemVerilog `` extension for macros 2018-05-17 00:09:56 -04:00
verilog_frontend.cc Include filename in "Executing Verilog-2005 frontend" message, fixes #959 2019-04-30 15:37:46 +02:00
verilog_frontend.h New behavior for front-end handling of whiteboxes 2019-04-20 22:24:50 +02:00
verilog_lexer.l Initial implementation of elaboration system tasks 2019-05-03 03:10:43 +03:00
verilog_parser.y Initial implementation of elaboration system tasks 2019-05-03 03:10:43 +03:00