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Code Activity
yosys/frontends/verilog
History
Zachary Snow f2c2d73f36 sv: fix up end label checking 
- disallow [gen]blocks with an end label but not begin label
- check validity of module end label
- fix memory leak of package name and end label
- fix memory leak of module end label
2021-06-16 21:48:05 -04:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
const2ast.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
Makefile.inc Treat all bison warnings as errors in verilog front-end 2020-07-15 11:57:31 +02:00
preproc.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
preproc.h Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
verilog_frontend.cc verilog: Squash a memory leak. 2021-06-14 17:07:41 +02:00
verilog_frontend.h verilog: Squash a memory leak. 2021-06-14 17:07:41 +02:00
verilog_lexer.l verilog: Squash a memory leak. 2021-06-14 17:07:41 +02:00
verilog_parser.y sv: fix up end label checking 2021-06-16 21:48:05 -04:00