mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-28 18:29:25 +00:00
1058 lines
24 KiB
Verilog
1058 lines
24 KiB
Verilog
(* abc9_lut=1, lib_whitebox *)
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module LUT4(input A, B, C, D, output Z);
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parameter INIT = "0x0000";
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`include "parse_init.vh"
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localparam initp = parse_init(INIT);
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wire [7:0] s3 = D ? initp[15:8] : initp[7:0];
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wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
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wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
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assign Z = A ? s1[1] : s1[0];
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// Per-input delay differences are considered 'interconnect'
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// so not known yet
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specify
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(A => Z) = 233;
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(B => Z) = 233;
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(C => Z) = 233;
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(D => Z) = 233;
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endspecify
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endmodule
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// This is a placeholder for ABC9 to extract the area/delay
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// cost of 5-input LUTs and is not intended to be instantiated
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(* abc9_lut=2 *)
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module \$__ABC9_LUT5 (input SEL, D, C, B, A, output Z);
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specify
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(SEL => Z) = 171;
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(D => Z) = 303;
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(C => Z) = 311;
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(B => Z) = 309;
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(A => Z) = 306;
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endspecify
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endmodule
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// Two LUT4s and MUX2
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module WIDEFN9(input A0, B0, C0, D0, A1, B1, C1, D1, SEL, output Z);
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parameter INIT0 = "0x0000";
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parameter INIT1 = "0x0000";
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wire z0, z1;
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LUT4 #(.INIT(INIT0)) lut4_0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(z0));
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LUT4 #(.INIT(INIT1)) lut4_1 (.A(A1), .B(B1), .C(C1), .D(D1), .Z(z1));
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assign Z = SEL ? z1 : z0;
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endmodule
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(* abc9_box, lib_whitebox *)
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module INV(input A, output Z);
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assign Z = !A;
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specify
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(A => Z) = 10;
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endspecify
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endmodule
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// Bidirectional IO buffer
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module BB(input T, I, output O,
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(* iopad_external_pin *) inout B);
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assign B = T ? 1'bz : I;
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assign O = B;
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endmodule
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// Input buffer
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module IB(
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(* iopad_external_pin *) input I,
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output O);
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assign O = I;
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endmodule
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// Output buffer
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module OB(input I,
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(* iopad_external_pin *) output O);
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assign O = I;
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endmodule
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// Output buffer with tristate
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module OBZ(input I, T,
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(* iopad_external_pin *) output O);
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assign O = T ? 1'bz : I;
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endmodule
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// Constants
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module VLO(output Z);
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assign Z = 1'b0;
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endmodule
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module VHI(output Z);
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assign Z = 1'b1;
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endmodule
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// Vendor flipflops
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// (all have active high clock, enable and set/reset - use INV to invert)
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// Async preset
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(* abc9_box, lib_whitebox *)
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module FD1P3BX(input D, CK, SP, PD, output reg Q);
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parameter GSR = "DISABLED";
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initial Q = 1'b1;
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always @(posedge CK or posedge PD)
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if (PD)
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Q <= 1'b1;
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else if (SP)
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Q <= D;
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specify
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$setup(D, posedge CK, 0);
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$setup(SP, posedge CK, 212);
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$setup(PD, posedge CK, 224);
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`ifndef YOSYS
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if (PD) (posedge CLK => (Q : 1)) = 0;
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`else
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if (PD) (PD => Q) = 0; // Technically, this should be an edge sensitive path
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// but for facilitating a bypass box, let's pretend it's
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// a simple path
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`endif
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if (!PD && SP) (posedge CK => (Q : D)) = 336;
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endspecify
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endmodule
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// Async clear
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(* abc9_box, lib_whitebox *)
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module FD1P3DX(input D, CK, SP, CD, output reg Q);
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parameter GSR = "DISABLED";
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initial Q = 1'b0;
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always @(posedge CK or posedge CD)
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if (CD)
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Q <= 1'b0;
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else if (SP)
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Q <= D;
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specify
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$setup(D, posedge CK, 0);
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$setup(SP, posedge CK, 212);
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$setup(CD, posedge CK, 224);
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`ifndef YOSYS
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if (CD) (posedge CLK => (Q : 0)) = 0;
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`else
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if (CD) (CD => Q) = 0; // Technically, this should be an edge sensitive path
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// but for facilitating a bypass box, let's pretend it's
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// a simple path
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`endif
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if (!CD && SP) (posedge CK => (Q : D)) = 336;
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endspecify
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endmodule
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// Sync clear
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(* abc9_flop, lib_whitebox *)
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module FD1P3IX(input D, CK, SP, CD, output reg Q);
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parameter GSR = "DISABLED";
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initial Q = 1'b0;
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always @(posedge CK)
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if (CD)
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Q <= 1'b0;
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else if (SP)
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Q <= D;
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specify
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$setup(D, posedge CK, 0);
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$setup(SP, posedge CK, 212);
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$setup(CD, posedge CK, 224);
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if (!CD && SP) (posedge CK => (Q : D)) = 336;
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endspecify
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endmodule
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// Sync preset
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(* abc9_flop, lib_whitebox *)
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module FD1P3JX(input D, CK, SP, PD, output reg Q);
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parameter GSR = "DISABLED";
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initial Q = 1'b1;
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always @(posedge CK)
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if (PD)
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Q <= 1'b1;
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else if (SP)
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Q <= D;
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specify
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$setup(D, posedge CK, 0);
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$setup(SP, posedge CK, 212);
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$setup(PD, posedge CK, 224);
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if (!PD && SP) (posedge CK => (Q : D)) = 336;
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endspecify
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endmodule
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// LUT4 with LUT3 tap for CCU2 use only
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(* lib_whitebox *)
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module LUT4_3(input A, B, C, D, output Z, Z3);
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parameter INIT = "0x0000";
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`include "parse_init.vh"
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localparam initp = parse_init(INIT);
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wire [7:0] s3 = D ? initp[15:8] : initp[7:0];
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wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
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wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
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assign Z = A ? s1[1] : s1[0];
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wire [3:0] s2_3 = C ? initp[ 7:4] : initp[3:0];
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wire [1:0] s1_3 = B ? s2_3[ 3:2] : s2_3[1:0];
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assign Z3 = A ? s1_3[1] : s1_3[0];
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endmodule
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// Carry primitive (incoporating two LUTs)
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(* abc9_box, lib_whitebox *)
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module CCU2(
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(* abc9_carry *) input CIN,
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input A1, B1, C1, D1, A0, B0, C0, D0,
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output S1, S0,
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(* abc9_carry *) output COUT);
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parameter INJECT = "YES";
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parameter INIT0 = "0x0000";
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parameter INIT1 = "0x1111";
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localparam inject_p = (INJECT == "YES") ? 1'b1 : 1'b0;
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wire LUT3_0, LUT4_0, LUT3_1, LUT4_1, carry_0;
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LUT4_3 #(.INIT(INIT0)) lut0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0), .Z3(LUT3_0));
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LUT4_3 #(.INIT(INIT1)) lut1 (.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1), .Z3(LUT3_1));
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assign S0 = LUT4_0 ^ (CIN & ~inject_p);
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assign carry_0 = LUT4_0 ? CIN : (LUT3_0 & ~inject_p);
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assign S1 = LUT4_1 ^ (carry_0 & ~inject_p);
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assign COUT = LUT4_1 ? carry_0 : (LUT3_1 & ~inject_p);
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specify
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(A0 => S0) = 233;
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(B0 => S0) = 233;
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(C0 => S0) = 233;
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(D0 => S0) = 233;
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(CIN => S0) = 228;
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(A0 => S1) = 481;
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(B0 => S1) = 481;
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(C0 => S1) = 481;
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(D0 => S1) = 481;
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(A1 => S1) = 233;
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(B1 => S1) = 233;
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(C1 => S1) = 233;
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(D1 => S1) = 233;
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(CIN => S1) = 307;
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(A0 => COUT) = 347;
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(B0 => COUT) = 347;
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(C0 => COUT) = 347;
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(D0 => COUT) = 347;
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(A1 => COUT) = 347;
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(B1 => COUT) = 347;
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(C1 => COUT) = 347;
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(D1 => COUT) = 347;
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(CIN => COUT) = 59;
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endspecify
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endmodule
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// Packed flipflop
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module OXIDE_FF(input CLK, LSR, CE, DI, M, output reg Q);
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parameter GSR = "ENABLED";
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parameter [127:0] CEMUX = "1";
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parameter CLKMUX = "CLK";
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parameter LSRMUX = "LSR";
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parameter REGDDR = "DISABLED";
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parameter SRMODE = "LSR_OVER_CE";
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parameter REGSET = "RESET";
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parameter [127:0] LSRMODE = "LSR";
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wire muxce;
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generate
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case (CEMUX)
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"1": assign muxce = 1'b1;
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"0": assign muxce = 1'b0;
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"INV": assign muxce = ~CE;
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default: assign muxce = CE;
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endcase
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endgenerate
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wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
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wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
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wire srval;
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generate
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if (LSRMODE == "PRLD")
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assign srval = M;
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else
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assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
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endgenerate
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initial Q = srval;
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generate
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if (REGDDR == "ENABLED") begin
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if (SRMODE == "ASYNC") begin
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always @(posedge muxclk, negedge muxclk, posedge muxlsr)
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if (muxlsr)
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Q <= srval;
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else if (muxce)
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Q <= DI;
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end else begin
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always @(posedge muxclk, negedge muxclk)
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if (muxlsr)
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Q <= srval;
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else if (muxce)
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Q <= DI;
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end
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end else begin
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if (SRMODE == "ASYNC") begin
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always @(posedge muxclk, posedge muxlsr)
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if (muxlsr)
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Q <= srval;
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else if (muxce)
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Q <= DI;
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end else begin
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always @(posedge muxclk)
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if (muxlsr)
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Q <= srval;
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else if (muxce)
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Q <= DI;
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end
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end
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endgenerate
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endmodule
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// Packed combinational logic (for post-pnr sim)
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module OXIDE_COMB(
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input A, B, C, D, // LUT inputs
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input SEL, // mux select input
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input F1, // output from LUT 1 for mux
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input FCI, // carry input
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input WAD0, WAD1, WAD2, WAD3, // LUTRAM write address inputs
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input WD, // LUTRAM write data input
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input WCK, WRE, // LUTRAM write clock and enable
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output F, // LUT/carry output
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output OFX // mux output
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);
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parameter MODE = "LOGIC"; // LOGIC, CCU2, DPRAM
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parameter [15:0] INIT = 16'h0000;
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parameter INJECT = "YES";
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localparam inject_p = (INJECT == "YES") ? 1'b1 : 1'b0;
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reg [15:0] lut = INIT;
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wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0];
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wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
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wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
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wire Z = A ? s1[1] : s1[0];
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wire [3:0] s2_3 = C ? INIT[ 7:4] : INIT[3:0];
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wire [1:0] s1_3 = B ? s2_3[ 3:2] : s2_3[1:0];
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wire Z3 = A ? s1_3[1] : s1_3[0];
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generate
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if (MODE == "DPRAM") begin
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always @(posedge WCK)
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if (WRE)
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lut[{WAD3, WAD2, WAD1, WAD0}] <= WD;
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end
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if (MODE == "CCU2") begin
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assign F = Z ^ (FCI & ~inject_p);
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assign FCO = Z ? FCI : (Z3 & ~inject_p);
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end else begin
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assign F = Z;
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end
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endgenerate
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assign OFX = SEL ? F1 : F;
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endmodule
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// LUTRAM
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module DPR16X4(
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input [3:0] RAD, DI, WAD,
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input WRE, WCK,
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output [3:0] DO
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);
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parameter INITVAL = "0x0000000000000000";
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`include "parse_init.vh"
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localparam [63:0] parsed_init = parse_init_64(INITVAL);
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reg [3:0] mem[0:15];
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integer i;
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initial begin
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for (i = 0; i < 15; i++)
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mem[i] = parsed_init[i * 4 +: 4];
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end
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always @(posedge WCK)
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if (WRE)
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mem[WAD] <= DI;
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assign DO = mem[RAD];
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endmodule
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// Used for all the DSP models to reduce duplication
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module OXIDE_DSP_REG #(
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parameter W = 18,
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parameter USED = "REGISTER",
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parameter RESETMODE = "SYNC"
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) (
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input CLK, CE, RST,
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input [W-1:0] D,
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output reg [W-1:0] Q
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);
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generate
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if (USED == "BYPASS")
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always @* Q = D;
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else if (USED == "REGISTER") begin
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initial Q = 0;
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if (RESETMODE == "ASYNC")
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always @(posedge CLK, posedge RST) begin
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if (RST)
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Q <= 0;
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else if (CE)
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Q <= D;
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end
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else if (RESETMODE == "SYNC")
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always @(posedge CLK) begin
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if (RST)
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Q <= 0;
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else if (CE)
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Q <= D;
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end
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end
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endgenerate
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endmodule
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module OXIDE_DSP_SIM #(
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// User facing parameters
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parameter REGINPUTA = "BYPASS",
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parameter REGINPUTB = "BYPASS",
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parameter REGINPUTC = "BYPASS",
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parameter REGADDSUB = "BYPASS",
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parameter REGLOADC = "BYPASS",
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parameter REGLOADC2 = "BYPASS",
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parameter REGCIN = "BYPASS",
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parameter REGPIPELINE = "BYPASS",
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parameter REGOUTPUT = "BYPASS",
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parameter GSR = "ENABLED",
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parameter RESETMODE = "SYNC",
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// Internally used parameters
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parameter A_WIDTH = 36,
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parameter B_WIDTH = 36,
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parameter C_WIDTH = 36,
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parameter Z_WIDTH = 72,
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parameter PREADD_USED = 0,
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parameter ADDSUB_USED = 0
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) (
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input [A_WIDTH-1:0] A,
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input [B_WIDTH-1:0] B,
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input [C_WIDTH-1:0] C,
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input SIGNEDA,
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input SIGNEDB,
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input SIGNEDC,
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input CIN,
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input LOADC,
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input ADDSUB,
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input CLK,
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input CEA, CEB, CEC, CEPIPE, CECTRL, CECIN, CEOUT,
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input RSTA, RSTB, RSTC, RSTPIPE, RSTCTRL, RSTCIN, RSTOUT,
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output wire [Z_WIDTH-1:0] Z
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);
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localparam M_WIDTH = (A_WIDTH+B_WIDTH);
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/******** REGISTERS ********/
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wire [M_WIDTH-1:0] pipe_d, pipe_q;
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wire [Z_WIDTH-1:0] z_d;
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wire [A_WIDTH-1:0] a_r;
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wire [B_WIDTH-1:0] b_r;
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wire [C_WIDTH-1:0] c_r, c_r2;
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wire asgd_r, bsgd_r, csgd_r, csgd_r2;
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wire addsub_r, addsub_r2, cin_r, cin_r2, sgd_r, sgd_r2;
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wire loadc_r, loadc_r2;
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OXIDE_DSP_REG #(A_WIDTH+1, REGINPUTA, RESETMODE) a_reg(CLK, CEA, RSTA, {SIGNEDA, A}, {asgd_r, a_r});
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OXIDE_DSP_REG #(B_WIDTH+1, REGINPUTB, RESETMODE) b_reg(CLK, CEB, RSTB, {SIGNEDB, B}, {bsgd_r, b_r});
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OXIDE_DSP_REG #(C_WIDTH+1, REGINPUTC, RESETMODE) c_reg(CLK, CEC, RSTC, {SIGNEDC, C}, {csgd_r, c_r});
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OXIDE_DSP_REG #(M_WIDTH, REGPIPELINE, RESETMODE) pipe_reg(CLK, CEPIPE, RSTPIPE, pipe_d, pipe_q);
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OXIDE_DSP_REG #(2, REGADDSUB, RESETMODE) addsub_reg(CLK, CECTRL, RSTCTRL, {SIGNEDA, ADDSUB}, {sgd_r, addsub_r});
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OXIDE_DSP_REG #(1, REGLOADC, RESETMODE) loadc_reg(CLK, CECTRL, RSTCTRL, LOADC, loadc_r);
|
|
OXIDE_DSP_REG #(2, REGPIPELINE, RESETMODE) addsub2_reg(CLK, CECTRL, RSTCTRL, {sgd_r, addsub_r}, {sgd_r2, addsub_r2});
|
|
OXIDE_DSP_REG #(1, REGLOADC2, RESETMODE) loadc2_reg(CLK, CECTRL, RSTCTRL, loadc_r, loadc_r2);
|
|
|
|
OXIDE_DSP_REG #(1, REGCIN, RESETMODE) cin_reg(CLK, CECIN, RSTCIN, CIN, cin_r);
|
|
OXIDE_DSP_REG #(1, REGPIPELINE, RESETMODE) cin2_reg(CLK, CECIN, RSTCIN, cin_r, cin_r2);
|
|
|
|
OXIDE_DSP_REG #(C_WIDTH+1, REGPIPELINE, RESETMODE) c2_reg(CLK, CEC, RSTC, {csgd_r, c_r}, {csgd_r2, c_r2});
|
|
|
|
OXIDE_DSP_REG #(Z_WIDTH, REGOUTPUT, RESETMODE) z_reg(CLK, CEOUT, RSTOUT, z_d, Z);
|
|
|
|
/******** PREADDER ********/
|
|
|
|
wire [B_WIDTH-1:0] mult_b;
|
|
wire mult_b_sgd;
|
|
|
|
generate
|
|
if (PREADD_USED) begin
|
|
assign mult_b = (b_r + c_r);
|
|
assign mult_b_sgd = (bsgd_r | csgd_r);
|
|
end else begin
|
|
assign mult_b = b_r;
|
|
assign mult_b_sgd = bsgd_r;
|
|
end
|
|
endgenerate
|
|
|
|
/******** MULTIPLIER ********/
|
|
|
|
// sign extend operands if needed
|
|
wire [M_WIDTH-1:0] mult_a_ext = {{(M_WIDTH-A_WIDTH){asgd_r ? a_r[A_WIDTH-1] : 1'b0}}, a_r};
|
|
wire [M_WIDTH-1:0] mult_b_ext = {{(M_WIDTH-B_WIDTH){mult_b_sgd ? mult_b[B_WIDTH-1] : 1'b0}}, mult_b};
|
|
|
|
wire [M_WIDTH-1:0] mult_m = mult_a_ext * mult_b_ext;
|
|
|
|
/******** ACCUMULATOR ********/
|
|
|
|
wire [Z_WIDTH-1:0] m_ext;
|
|
|
|
generate
|
|
if (ADDSUB_USED) begin
|
|
assign pipe_d = mult_m;
|
|
assign m_ext = {{(Z_WIDTH-M_WIDTH){sgd_r2 ? pipe_q[M_WIDTH-1] : 1'b0}}, pipe_q};
|
|
assign z_d = (loadc_r2 ? c_r2 : Z) + cin_r2 + (addsub_r2 ? -m_ext : m_ext);
|
|
end else begin
|
|
assign z_d = mult_m;
|
|
end
|
|
endgenerate
|
|
|
|
|
|
endmodule
|
|
|
|
module MULT9X9 #(
|
|
parameter REGINPUTA = "REGISTER",
|
|
parameter REGINPUTB = "REGISTER",
|
|
parameter REGOUTPUT = "REGISTER",
|
|
parameter GSR = "ENABLED",
|
|
parameter RESETMODE = "SYNC"
|
|
) (
|
|
input [8:0] A,
|
|
input [8:0] B,
|
|
input CLK,
|
|
input CEA,
|
|
input RSTA,
|
|
input CEB,
|
|
input RSTB,
|
|
input SIGNEDA,
|
|
input SIGNEDB,
|
|
input RSTOUT,
|
|
input CEOUT,
|
|
output [17:0] Z
|
|
);
|
|
OXIDE_DSP_SIM #(
|
|
.REGINPUTA(REGINPUTA),
|
|
.REGINPUTB(REGINPUTB),
|
|
.REGOUTPUT(REGOUTPUT),
|
|
.GSR(GSR),
|
|
.RESETMODE(RESETMODE),
|
|
|
|
.A_WIDTH(9),
|
|
.B_WIDTH(9),
|
|
.Z_WIDTH(18),
|
|
.PREADD_USED(0),
|
|
.ADDSUB_USED(0)
|
|
) dsp_i (
|
|
.A(A), .B(B),
|
|
.CLK(CLK),
|
|
.CEA(CEA), .RSTA(RSTA),
|
|
.CEB(CEB), .RSTB(RSTB),
|
|
.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB),
|
|
.RSTOUT(RSTOUT), .CEOUT(CEOUT),
|
|
.Z(Z)
|
|
);
|
|
endmodule
|
|
|
|
module MULT18X18 #(
|
|
parameter REGINPUTA = "REGISTER",
|
|
parameter REGINPUTB = "REGISTER",
|
|
parameter REGOUTPUT = "REGISTER",
|
|
parameter GSR = "ENABLED",
|
|
parameter RESETMODE = "SYNC"
|
|
) (
|
|
input [17:0] A,
|
|
input [17:0] B,
|
|
input CLK,
|
|
input CEA,
|
|
input RSTA,
|
|
input CEB,
|
|
input RSTB,
|
|
input SIGNEDA,
|
|
input SIGNEDB,
|
|
input RSTOUT,
|
|
input CEOUT,
|
|
output [35:0] Z
|
|
);
|
|
OXIDE_DSP_SIM #(
|
|
.REGINPUTA(REGINPUTA),
|
|
.REGINPUTB(REGINPUTB),
|
|
.REGOUTPUT(REGOUTPUT),
|
|
.GSR(GSR),
|
|
.RESETMODE(RESETMODE),
|
|
|
|
.A_WIDTH(18),
|
|
.B_WIDTH(18),
|
|
.Z_WIDTH(36),
|
|
.PREADD_USED(0),
|
|
.ADDSUB_USED(0)
|
|
) dsp_i (
|
|
.A(A), .B(B),
|
|
.CLK(CLK),
|
|
.CEA(CEA), .RSTA(RSTA),
|
|
.CEB(CEB), .RSTB(RSTB),
|
|
.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB),
|
|
.RSTOUT(RSTOUT), .CEOUT(CEOUT),
|
|
.Z(Z)
|
|
);
|
|
endmodule
|
|
|
|
module MULT18X36 #(
|
|
parameter REGINPUTA = "REGISTER",
|
|
parameter REGINPUTB = "REGISTER",
|
|
parameter REGOUTPUT = "REGISTER",
|
|
parameter GSR = "ENABLED",
|
|
parameter RESETMODE = "SYNC"
|
|
) (
|
|
input [17:0] A,
|
|
input [35:0] B,
|
|
input CLK,
|
|
input CEA,
|
|
input RSTA,
|
|
input CEB,
|
|
input RSTB,
|
|
input SIGNEDA,
|
|
input SIGNEDB,
|
|
input RSTOUT,
|
|
input CEOUT,
|
|
output [53:0] Z
|
|
);
|
|
OXIDE_DSP_SIM #(
|
|
.REGINPUTA(REGINPUTA),
|
|
.REGINPUTB(REGINPUTB),
|
|
.REGOUTPUT(REGOUTPUT),
|
|
.GSR(GSR),
|
|
.RESETMODE(RESETMODE),
|
|
|
|
.A_WIDTH(18),
|
|
.B_WIDTH(36),
|
|
.Z_WIDTH(54),
|
|
.PREADD_USED(0),
|
|
.ADDSUB_USED(0)
|
|
) dsp_i (
|
|
.A(A), .B(B),
|
|
.CLK(CLK),
|
|
.CEA(CEA), .RSTA(RSTA),
|
|
.CEB(CEB), .RSTB(RSTB),
|
|
.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB),
|
|
.RSTOUT(RSTOUT), .CEOUT(CEOUT),
|
|
.Z(Z)
|
|
);
|
|
endmodule
|
|
|
|
module MULT36X36 #(
|
|
parameter REGINPUTA = "REGISTER",
|
|
parameter REGINPUTB = "REGISTER",
|
|
parameter REGOUTPUT = "REGISTER",
|
|
parameter GSR = "ENABLED",
|
|
parameter RESETMODE = "SYNC"
|
|
) (
|
|
input [35:0] A,
|
|
input [35:0] B,
|
|
input CLK,
|
|
input CEA,
|
|
input RSTA,
|
|
input CEB,
|
|
input RSTB,
|
|
input SIGNEDA,
|
|
input SIGNEDB,
|
|
input RSTOUT,
|
|
input CEOUT,
|
|
output [71:0] Z
|
|
);
|
|
OXIDE_DSP_SIM #(
|
|
.REGINPUTA(REGINPUTA),
|
|
.REGINPUTB(REGINPUTB),
|
|
.REGOUTPUT(REGOUTPUT),
|
|
.GSR(GSR),
|
|
.RESETMODE(RESETMODE),
|
|
|
|
.A_WIDTH(36),
|
|
.B_WIDTH(36),
|
|
.Z_WIDTH(72),
|
|
.PREADD_USED(0),
|
|
.ADDSUB_USED(0)
|
|
) dsp_i (
|
|
.A(A), .B(B),
|
|
.CLK(CLK),
|
|
.CEA(CEA), .RSTA(RSTA),
|
|
.CEB(CEB), .RSTB(RSTB),
|
|
.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB),
|
|
.RSTOUT(RSTOUT), .CEOUT(CEOUT),
|
|
.Z(Z)
|
|
);
|
|
endmodule
|
|
|
|
|
|
module MULTPREADD9X9 #(
|
|
parameter REGINPUTA = "REGISTER",
|
|
parameter REGINPUTB = "REGISTER",
|
|
parameter REGINPUTC = "REGISTER",
|
|
parameter REGOUTPUT = "REGISTER",
|
|
parameter GSR = "ENABLED",
|
|
parameter RESETMODE = "SYNC"
|
|
) (
|
|
input [8:0] A,
|
|
input [8:0] B,
|
|
input [8:0] C,
|
|
input CLK,
|
|
input CEA,
|
|
input RSTA,
|
|
input CEB,
|
|
input RSTB,
|
|
input CEC,
|
|
input RSTC,
|
|
input SIGNEDA,
|
|
input SIGNEDB,
|
|
input SIGNEDC,
|
|
input RSTOUT,
|
|
input CEOUT,
|
|
output [17:0] Z
|
|
);
|
|
OXIDE_DSP_SIM #(
|
|
.REGINPUTA(REGINPUTA),
|
|
.REGINPUTB(REGINPUTB),
|
|
.REGINPUTC(REGINPUTC),
|
|
.REGOUTPUT(REGOUTPUT),
|
|
.GSR(GSR),
|
|
.RESETMODE(RESETMODE),
|
|
|
|
.A_WIDTH(9),
|
|
.B_WIDTH(9),
|
|
.C_WIDTH(9),
|
|
.Z_WIDTH(18),
|
|
.PREADD_USED(1),
|
|
.ADDSUB_USED(0)
|
|
) dsp_i (
|
|
.A(A), .B(B), .C(C),
|
|
.CLK(CLK),
|
|
.CEA(CEA), .RSTA(RSTA),
|
|
.CEB(CEB), .RSTB(RSTB),
|
|
.CEC(CEC), .RSTC(RSTC),
|
|
.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB), .SIGNEDC(SIGNEDC),
|
|
.RSTOUT(RSTOUT), .CEOUT(CEOUT),
|
|
.Z(Z)
|
|
);
|
|
endmodule
|
|
|
|
|
|
module MULTPREADD18X18 #(
|
|
parameter REGINPUTA = "REGISTER",
|
|
parameter REGINPUTB = "REGISTER",
|
|
parameter REGINPUTC = "REGISTER",
|
|
parameter REGOUTPUT = "REGISTER",
|
|
parameter GSR = "ENABLED",
|
|
parameter RESETMODE = "SYNC"
|
|
) (
|
|
input [17:0] A,
|
|
input [17:0] B,
|
|
input [17:0] C,
|
|
input CLK,
|
|
input CEA,
|
|
input RSTA,
|
|
input CEB,
|
|
input RSTB,
|
|
input CEC,
|
|
input RSTC,
|
|
input SIGNEDA,
|
|
input SIGNEDB,
|
|
input SIGNEDC,
|
|
input RSTOUT,
|
|
input CEOUT,
|
|
output [35:0] Z
|
|
);
|
|
OXIDE_DSP_SIM #(
|
|
.REGINPUTA(REGINPUTA),
|
|
.REGINPUTB(REGINPUTB),
|
|
.REGINPUTC(REGINPUTC),
|
|
.REGOUTPUT(REGOUTPUT),
|
|
.GSR(GSR),
|
|
.RESETMODE(RESETMODE),
|
|
|
|
.A_WIDTH(18),
|
|
.B_WIDTH(18),
|
|
.C_WIDTH(18),
|
|
.Z_WIDTH(36),
|
|
.PREADD_USED(1),
|
|
.ADDSUB_USED(0)
|
|
) dsp_i (
|
|
.A(A), .B(B), .C(C),
|
|
.CLK(CLK),
|
|
.CEA(CEA), .RSTA(RSTA),
|
|
.CEB(CEB), .RSTB(RSTB),
|
|
.CEC(CEC), .RSTC(RSTC),
|
|
.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB), .SIGNEDC(SIGNEDC),
|
|
.RSTOUT(RSTOUT), .CEOUT(CEOUT),
|
|
.Z(Z)
|
|
);
|
|
endmodule
|
|
|
|
|
|
module MULTADDSUB18X18 #(
|
|
parameter REGINPUTA = "REGISTER",
|
|
parameter REGINPUTB = "REGISTER",
|
|
parameter REGINPUTC = "REGISTER",
|
|
parameter REGADDSUB = "REGISTER",
|
|
parameter REGLOADC = "REGISTER",
|
|
parameter REGLOADC2 = "REGISTER",
|
|
parameter REGCIN = "REGISTER",
|
|
parameter REGPIPELINE = "REGISTER",
|
|
parameter REGOUTPUT = "REGISTER",
|
|
parameter GSR = "ENABLED",
|
|
parameter RESETMODE = "SYNC"
|
|
) (
|
|
input [17:0] A,
|
|
input [17:0] B,
|
|
input [53:0] C,
|
|
input CLK,
|
|
input CEA,
|
|
input RSTA,
|
|
input CEB,
|
|
input RSTB,
|
|
input CEC,
|
|
input RSTC,
|
|
input SIGNED,
|
|
input RSTPIPE,
|
|
input CEPIPE,
|
|
input RSTCTRL,
|
|
input CECTRL,
|
|
input RSTCIN,
|
|
input CECIN,
|
|
input LOADC,
|
|
input ADDSUB,
|
|
output [53:0] Z,
|
|
input RSTOUT,
|
|
input CEOUT,
|
|
input CIN
|
|
);
|
|
OXIDE_DSP_SIM #(
|
|
.REGINPUTA(REGINPUTA),
|
|
.REGINPUTB(REGINPUTB),
|
|
.REGINPUTC(REGINPUTC),
|
|
.REGADDSUB(REGADDSUB),
|
|
.REGLOADC(REGLOADC),
|
|
.REGLOADC2(REGLOADC2),
|
|
.REGCIN(REGCIN),
|
|
.REGPIPELINE(REGPIPELINE),
|
|
.REGOUTPUT(REGOUTPUT),
|
|
.GSR(GSR),
|
|
.RESETMODE(RESETMODE),
|
|
|
|
.A_WIDTH(18),
|
|
.B_WIDTH(18),
|
|
.C_WIDTH(54),
|
|
.Z_WIDTH(54),
|
|
.PREADD_USED(0),
|
|
.ADDSUB_USED(1)
|
|
) dsp_i (
|
|
.A(A), .B(B), .C(C),
|
|
.CLK(CLK),
|
|
.CEA(CEA), .RSTA(RSTA),
|
|
.CEB(CEB), .RSTB(RSTB),
|
|
.CEC(CEC), .RSTC(RSTC),
|
|
.CEPIPE(CEPIPE), .RSTPIPE(RSTPIPE),
|
|
.CECTRL(CECTRL), .RSTCTRL(RSTCTRL),
|
|
.CECIN(CECIN), .RSTCIN(RSTCIN),
|
|
.CIN(CIN), .LOADC(LOADC), .ADDSUB(ADDSUB),
|
|
.SIGNEDA(SIGNED), .SIGNEDB(SIGNED), .SIGNEDC(SIGNED),
|
|
.RSTOUT(RSTOUT), .CEOUT(CEOUT),
|
|
.Z(Z)
|
|
);
|
|
endmodule
|
|
|
|
|
|
module MULTADDSUB36X36 #(
|
|
parameter REGINPUTA = "REGISTER",
|
|
parameter REGINPUTB = "REGISTER",
|
|
parameter REGINPUTC = "REGISTER",
|
|
parameter REGADDSUB = "REGISTER",
|
|
parameter REGLOADC = "REGISTER",
|
|
parameter REGLOADC2 = "REGISTER",
|
|
parameter REGCIN = "REGISTER",
|
|
parameter REGPIPELINE = "REGISTER",
|
|
parameter REGOUTPUT = "REGISTER",
|
|
parameter GSR = "ENABLED",
|
|
parameter RESETMODE = "SYNC"
|
|
) (
|
|
input [35:0] A,
|
|
input [35:0] B,
|
|
input [107:0] C,
|
|
input CLK,
|
|
input CEA,
|
|
input RSTA,
|
|
input CEB,
|
|
input RSTB,
|
|
input CEC,
|
|
input RSTC,
|
|
input SIGNED,
|
|
input RSTPIPE,
|
|
input CEPIPE,
|
|
input RSTCTRL,
|
|
input CECTRL,
|
|
input RSTCIN,
|
|
input CECIN,
|
|
input LOADC,
|
|
input ADDSUB,
|
|
output [107:0] Z,
|
|
input RSTOUT,
|
|
input CEOUT,
|
|
input CIN
|
|
);
|
|
OXIDE_DSP_SIM #(
|
|
.REGINPUTA(REGINPUTA),
|
|
.REGINPUTB(REGINPUTB),
|
|
.REGINPUTC(REGINPUTC),
|
|
.REGADDSUB(REGADDSUB),
|
|
.REGLOADC(REGLOADC),
|
|
.REGLOADC2(REGLOADC2),
|
|
.REGCIN(REGCIN),
|
|
.REGPIPELINE(REGPIPELINE),
|
|
.REGOUTPUT(REGOUTPUT),
|
|
.GSR(GSR),
|
|
.RESETMODE(RESETMODE),
|
|
|
|
.A_WIDTH(36),
|
|
.B_WIDTH(36),
|
|
.C_WIDTH(108),
|
|
.Z_WIDTH(108),
|
|
.PREADD_USED(0),
|
|
.ADDSUB_USED(1)
|
|
) dsp_i (
|
|
.A(A), .B(B), .C(C),
|
|
.CLK(CLK),
|
|
.CEA(CEA), .RSTA(RSTA),
|
|
.CEB(CEB), .RSTB(RSTB),
|
|
.CEC(CEC), .RSTC(RSTC),
|
|
.CEPIPE(CEPIPE), .RSTPIPE(RSTPIPE),
|
|
.CECTRL(CECTRL), .RSTCTRL(RSTCTRL),
|
|
.CECIN(CECIN), .RSTCIN(RSTCIN),
|
|
.CIN(CIN), .LOADC(LOADC), .ADDSUB(ADDSUB),
|
|
.SIGNEDA(SIGNED), .SIGNEDB(SIGNED), .SIGNEDC(SIGNED),
|
|
.RSTOUT(RSTOUT), .CEOUT(CEOUT),
|
|
.Z(Z)
|
|
);
|
|
endmodule
|
|
|
|
module MULTADDSUB9X9WIDE #(
|
|
parameter REGINPUTAB0 = "REGISTER",
|
|
parameter REGINPUTAB1 = "REGISTER",
|
|
parameter REGINPUTAB2 = "REGISTER",
|
|
parameter REGINPUTAB3 = "REGISTER",
|
|
parameter REGINPUTC = "REGISTER",
|
|
parameter REGADDSUB = "REGISTER",
|
|
parameter REGLOADC = "REGISTER",
|
|
parameter REGLOADC2 = "REGISTER",
|
|
parameter REGPIPELINE = "REGISTER",
|
|
parameter REGOUTPUT = "REGISTER",
|
|
parameter GSR = "ENABLED",
|
|
parameter RESETMODE = "SYNC"
|
|
) (
|
|
input [8:0] A0, B0, A1, B1, A2, B2, A3, B3,
|
|
input [53:0] C,
|
|
input CLK,
|
|
input CEA0A1, CEA2A3,
|
|
input RSTA0A1, RSTA2A3,
|
|
input CEB0B1, CEB2B3,
|
|
input RSTB0B1, RSTB2B3,
|
|
input CEC, RSTC,
|
|
input CECTRL, RSTCTRL,
|
|
input SIGNED,
|
|
input RSTPIPE, CEPIPE,
|
|
input RSTOUT, CEOUT,
|
|
input LOADC,
|
|
input [3:0] ADDSUB,
|
|
output [53:0] Z
|
|
);
|
|
wire [17:0] m0, m1, m2, m3;
|
|
|
|
localparam M_WIDTH = 18;
|
|
localparam Z_WIDTH = 54;
|
|
|
|
MULT9X9 #(
|
|
.REGINPUTA(REGINPUTAB0), .REGINPUTB(REGINPUTAB0), .REGOUTPUT(REGPIPELINE), .GSR(GSR), .RESETMODE(RESETMODE)
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) m9_0 (
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.A(A0), .B(B0), .SIGNEDA(SIGNED), .SIGNEDB(SIGNED),
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.CLK(CLK),
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.CEA(CEA0A1), .RSTA(RSTA0A1),
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.CEB(CEB0B1), .RSTB(RSTB0B1),
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.CEOUT(CEPIPE), .RSTOUT(RSTPIPE),
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.Z(m0)
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);
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MULT9X9 #(
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.REGINPUTA(REGINPUTAB1), .REGINPUTB(REGINPUTAB1), .REGOUTPUT(REGPIPELINE), .GSR(GSR), .RESETMODE(RESETMODE)
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) m9_1 (
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.A(A1), .B(B1), .SIGNEDA(SIGNED), .SIGNEDB(SIGNED),
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.CLK(CLK),
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.CEA(CEA0A1), .RSTA(RSTA0A1),
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.CEB(CEB0B1), .RSTB(RSTB0B1),
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.CEOUT(CEPIPE), .RSTOUT(RSTPIPE),
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.Z(m1)
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);
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MULT9X9 #(
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.REGINPUTA(REGINPUTAB2), .REGINPUTB(REGINPUTAB2), .REGOUTPUT(REGPIPELINE), .GSR(GSR), .RESETMODE(RESETMODE)
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) m9_2 (
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.A(A2), .B(B2), .SIGNEDA(SIGNED), .SIGNEDB(SIGNED),
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.CLK(CLK),
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.CEA(CEA2A3), .RSTA(RSTA2A3),
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.CEB(CEB2B3), .RSTB(RSTB2B3),
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.CEOUT(CEPIPE), .RSTOUT(RSTPIPE),
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.Z(m2)
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);
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MULT9X9 #(
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.REGINPUTA(REGINPUTAB3), .REGINPUTB(REGINPUTAB3), .REGOUTPUT(REGPIPELINE), .GSR(GSR), .RESETMODE(RESETMODE)
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) m9_3 (
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.A(A3), .B(B3), .SIGNEDA(SIGNED), .SIGNEDB(SIGNED),
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.CLK(CLK),
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.CEA(CEA2A3), .RSTA(RSTA2A3),
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.CEB(CEB2B3), .RSTB(RSTB2B3),
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.CEOUT(CEPIPE), .RSTOUT(RSTPIPE),
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.Z(m3)
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);
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wire [53:0] c_r, c_r2;
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wire [3:0] addsub_r, addsub_r2;
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wire sgd_r, sgd_r2, csgd_r, csgd_r2;
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wire loadc_r, loadc_r2;
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OXIDE_DSP_REG #(5, REGADDSUB, RESETMODE) addsub_reg(CLK, CECTRL, RSTCTRL, {SIGNED, ADDSUB}, {sgd_r, addsub_r});
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OXIDE_DSP_REG #(5, REGADDSUB, RESETMODE) addsub2_reg(CLK, CECTRL, RSTCTRL, {sgd_r, addsub_r}, {sgd_r2, addsub_r2});
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OXIDE_DSP_REG #(1, REGLOADC, RESETMODE) loadc_reg(CLK, CECTRL, RSTCTRL, LOADC, loadc_r);
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OXIDE_DSP_REG #(1, REGLOADC2, RESETMODE) loadc2_reg(CLK, CECTRL, RSTCTRL, loadc_r, loadc_r2);
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OXIDE_DSP_REG #(55, REGINPUTC, RESETMODE) c_reg(CLK, CEC, RSTC, {SIGNED, C}, {csgd_r, c_r});
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OXIDE_DSP_REG #(55, REGPIPELINE, RESETMODE) c2_reg(CLK, CEC, RSTC, {csgd_r, c_r}, {csgd_r2, c_r2});
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|
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wire [18:0] m0_ext, m1_ext, m2_ext, m3_ext;
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assign m0_ext = {sgd_r2 ? m0[M_WIDTH-1] : 1'b0, m0};
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assign m1_ext = {sgd_r2 ? m1[M_WIDTH-1] : 1'b0, m1};
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assign m2_ext = {sgd_r2 ? m2[M_WIDTH-1] : 1'b0, m2};
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assign m3_ext = {sgd_r2 ? m3[M_WIDTH-1] : 1'b0, m3};
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|
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wire [18:0] s0 = addsub_r2[2] ? (m0_ext - m1_ext) : (m0_ext + m1_ext);
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wire [18:0] s1 = addsub_r2[3] ? (m2_ext - m3_ext) : (m2_ext + m3_ext);
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|
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wire [53:0] s0_ext = {{(54-19){sgd_r2 ? s0[18] : 1'b0}}, s0};
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|
wire [53:0] s1_ext = {{(54-19){sgd_r2 ? s1[18] : 1'b0}}, s1};
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|
|
|
wire [53:0] c_op = loadc_r2 ? c_r2 : Z;
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|
|
|
// The diagram in the docs is wrong! It is not two cascaded 2-input add/subs as shown,
|
|
// but a three-input unit with negation controls on two inputs (i.e. addsub_r2[0]
|
|
// negates s1 not (s1 +/- s0))
|
|
wire [53:0] z_d = c_op + (addsub_r2[0] ? -s1_ext : s1_ext) + (addsub_r2[1] ? -s0_ext : s0_ext);
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|
|
|
OXIDE_DSP_REG #(Z_WIDTH, REGOUTPUT, RESETMODE) z_reg(CLK, CEOUT, RSTOUT, z_d, Z);
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|
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|
endmodule
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