mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
258 lines
8.4 KiB
C++
258 lines
8.4 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* (C) 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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#include "passes/pmgen/xilinx_srl_pm.h"
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void run_fixed(xilinx_srl_pm &pm)
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{
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auto &st = pm.st_fixed;
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auto &ud = pm.ud_fixed;
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log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type));
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SigSpec initval;
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for (auto cell : ud.longest_chain) {
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log_debug(" %s\n", log_id(cell));
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if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) {
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SigBit Q = cell->getPort(ID::Q);
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log_assert(Q.wire);
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auto it = Q.wire->attributes.find(ID::init);
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if (it != Q.wire->attributes.end()) {
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auto &i = it->second[Q.offset];
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initval.append(i);
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i = State::Sx;
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}
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else
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initval.append(State::Sx);
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}
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else if (cell->type.in(ID(FDRE), ID(FDRE_1))) {
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if (cell->getParam(ID::INIT).as_bool())
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initval.append(State::S1);
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else
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initval.append(State::S0);
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}
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else
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log_abort();
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pm.autoremove(cell);
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}
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auto first_cell = ud.longest_chain.back();
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auto last_cell = ud.longest_chain.front();
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Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_));
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pm.module->swap_names(c, first_cell);
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if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
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c->setParam(ID::DEPTH, GetSize(ud.longest_chain));
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c->setParam(ID::INIT, initval.as_const());
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if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
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c->setParam(ID(CLKPOL), 1);
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else if (first_cell->type.in(ID($_DFF_N_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1)))
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c->setParam(ID(CLKPOL), 0);
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else if (first_cell->type.in(ID(FDRE))) {
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if (!first_cell->getParam(ID(IS_C_INVERTED)).as_bool())
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c->setParam(ID(CLKPOL), 1);
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else
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c->setParam(ID(CLKPOL), 0);
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}
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else
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log_abort();
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if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
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c->setParam(ID(ENPOL), 1);
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else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
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c->setParam(ID(ENPOL), 0);
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else
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c->setParam(ID(ENPOL), 2);
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c->setPort(ID::C, first_cell->getPort(ID::C));
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c->setPort(ID::D, first_cell->getPort(ID::D));
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c->setPort(ID::Q, last_cell->getPort(ID::Q));
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c->setPort(ID::L, GetSize(ud.longest_chain)-1);
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if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
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c->setPort(ID::E, State::S1);
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else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
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c->setPort(ID::E, first_cell->getPort(ID::E));
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else if (first_cell->type.in(ID(FDRE), ID(FDRE_1)))
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c->setPort(ID::E, first_cell->getPort(ID(CE)));
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else
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log_abort();
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}
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else
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log_abort();
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log(" -> %s (%s)\n", log_id(c), log_id(c->type));
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}
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void run_variable(xilinx_srl_pm &pm)
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{
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auto &st = pm.st_variable;
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auto &ud = pm.ud_variable;
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log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), log_id(st.first->type));
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SigSpec initval;
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for (const auto &i : ud.chain) {
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auto cell = i.first;
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auto slice = i.second;
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log_debug(" %s\n", log_id(cell));
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if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
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SigBit Q = cell->getPort(ID::Q)[slice];
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log_assert(Q.wire);
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auto it = Q.wire->attributes.find(ID::init);
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if (it != Q.wire->attributes.end()) {
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auto &i = it->second[Q.offset];
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initval.append(i);
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i = State::Sx;
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}
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else
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initval.append(State::Sx);
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}
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else
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log_abort();
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}
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pm.autoremove(st.shiftx);
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auto first_cell = ud.chain.back().first;
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auto first_slice = ud.chain.back().second;
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Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_));
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pm.module->swap_names(c, first_cell);
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if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
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c->setParam(ID::DEPTH, GetSize(ud.chain));
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c->setParam(ID::INIT, initval.as_const());
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Const clkpol, enpol;
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if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
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clkpol = 1;
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else if (first_cell->type.in(ID($_DFF_N_), ID($_DFFE_NN_), ID($_DFFE_NP_)))
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clkpol = 0;
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else if (first_cell->type.in(ID($dff), ID($dffe)))
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clkpol = first_cell->getParam(ID::CLK_POLARITY);
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else
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log_abort();
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if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
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enpol = 1;
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else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
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enpol = 0;
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else if (first_cell->type.in(ID($dffe)))
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enpol = first_cell->getParam(ID::EN_POLARITY);
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else
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enpol = 2;
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c->setParam(ID(CLKPOL), clkpol);
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c->setParam(ID(ENPOL), enpol);
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if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
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c->setPort(ID::C, first_cell->getPort(ID::C));
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else if (first_cell->type.in(ID($dff), ID($dffe)))
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c->setPort(ID::C, first_cell->getPort(ID::CLK));
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else
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log_abort();
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c->setPort(ID::D, first_cell->getPort(ID::D)[first_slice]);
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c->setPort(ID::Q, st.shiftx->getPort(ID::Y));
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c->setPort(ID::L, st.shiftx->getPort(ID::B));
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if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($dff)))
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c->setPort(ID::E, State::S1);
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else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
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c->setPort(ID::E, first_cell->getPort(ID::E));
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else if (first_cell->type.in(ID($dffe)))
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c->setPort(ID::E, first_cell->getPort(ID::EN));
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else
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log_abort();
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}
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else
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log_abort();
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log(" -> %s (%s)\n", log_id(c), log_id(c->type));
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}
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struct XilinxSrlPass : public Pass {
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XilinxSrlPass() : Pass("xilinx_srl", "Xilinx shift register extraction") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" xilinx_srl [options] [selection]\n");
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log("\n");
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log("This pass converts chains of built-in flops (bit-level: $_DFF_[NP]_, $_DFFE_*\n");
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log("and word-level: $dff, $dffe) as well as Xilinx flops (FDRE, FDRE_1) into a\n");
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log("$__XILINX_SHREG cell. Chains must be of the same cell type, clock, clock polarity,\n");
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log("enable, and enable polarity (where relevant).\n");
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log("Flops with resets cannot be mapped to Xilinx devices and will not be inferred.");
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log("\n");
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log(" -minlen N\n");
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log(" min length of shift register (default = 3)\n");
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log("\n");
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log(" -fixed\n");
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log(" infer fixed-length shift registers.\n");
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log("\n");
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log(" -variable\n");
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log(" infer variable-length shift registers (i.e. fixed-length shifts where\n");
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log(" each element also fans-out to a $shiftx cell).\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing XILINX_SRL pass (Xilinx shift register extraction).\n");
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bool fixed = false;
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bool variable = false;
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int minlen = 3;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-minlen" && argidx+1 < args.size()) {
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minlen = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-fixed") {
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fixed = true;
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continue;
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}
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if (args[argidx] == "-variable") {
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variable = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!fixed && !variable)
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log_cmd_error("'-fixed' and/or '-variable' must be specified.\n");
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for (auto module : design->selected_modules()) {
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auto pm = xilinx_srl_pm(module, module->selected_cells());
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pm.ud_fixed.minlen = minlen;
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pm.ud_variable.minlen = minlen;
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if (fixed)
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pm.run_fixed(run_fixed);
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if (variable)
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pm.run_variable(run_variable);
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}
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}
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} XilinxSrlPass;
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PRIVATE_NAMESPACE_END
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