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yosys/techlibs/gowin
2019-11-11 17:51:26 +01:00
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arith_map.v
bram.txt
brams_init.py
brams_init3.vh
brams_map.v
cells_map.v fix fsm test with proper clock enable polarity 2019-11-11 17:51:26 +01:00
cells_sim.v
determine_init.cc
dram.txt
drams_map.v
Makefile.inc
synth_gowin.cc