Emil J a78eb9e151 Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort ... write_rtlil: don't sort		2025-09-22 11:14:39 +02:00
..
choices	Merge pull request #4789 from YosysHQ/emil/sklansky-adder	2024-12-03 11:33:13 +01:00
.gitignore
abc9_map.v
abc9_model.v
abc9_unmap.v
adff2dff.v
cellhelp.py
cells.lib
cmp2lcu.v
cmp2lut.v
cmp2softlogic.v
dff2ff.v
gate2lut.v
gen_fine_ffs.py
Makefile.inc
mul2dsp.v
pmux2mux.v
prep.cc	Remove .c_str() from stringf parameters	2025-09-01 23:34:42 +00:00
simcells.v
simlib.v	Add $input_port and $connect cell types	2025-09-17 13:56:46 +02:00
smtmap.v
synth.cc	read_verilog: add -relativeshare for synthesis reproducibility testing	2025-09-16 15:47:35 +02:00
techmap.v	Add $input_port and $connect cell types	2025-09-17 13:56:46 +02:00