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aa9b86aeec
yosys
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frontends
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Miodrag Milanovic
d473a207a1
Preserve VHDL architecture name in attribute
2023-10-12 09:17:06 +02:00
..
aiger
ast
ast/simplify: Remove unused in_param code
2023-10-05 22:42:36 -04:00
blif
json
liberty
rpc
rtlil
verific
Preserve VHDL architecture name in attribute
2023-10-12 09:17:06 +02:00
verilog