Miodrag Milanovic a689342207 Remove trailing whitespaces		2026-06-23 07:24:59 +02:00
..
tb	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
.gitignore
adff.v
adffe.v
adlatch.v
aldff.v
aldffe.v
assume_x_first_step.ys	End of file fix	2026-06-23 07:23:41 +02:00
dff.v
dffe.v
dffsr.v
dlatch.v
dlatchsr.v
generate_mk.py	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
sdff.v
sdffce.v
sdffe.v
sim_adff.ys
sim_adffe.ys
sim_adlatch.ys
sim_aldff.ys
sim_aldffe.ys
sim_cycles.ys	Revert sim's cycle_width default back to 10, but keep -width option	2025-10-20 14:40:05 +02:00
sim_dff.ys
sim_dffe.ys
sim_dffsr.ys
sim_dlatch.ys
sim_dlatchsr.ys
sim_sdff.ys
sim_sdffce.ys
sim_sdffe.ys
simple_assign.v
simple_assign.vcd	End of file fix	2026-06-23 07:23:41 +02:00
undriven_replay.v	Detect undriven and error/warn	2026-02-20 11:00:59 -08:00
undriven_replay.vcd	Detect undriven and error/warn	2026-02-20 11:00:59 -08:00
undriven_replay.ys	Expand test into three tests for three cases	2026-02-23 10:27:36 -08:00
undriven_replay_nocheck.ys	Expand test into three tests for three cases	2026-02-23 10:27:36 -08:00
undriven_replay_warn.ys	Expand test into three tests for three cases	2026-02-23 10:27:36 -08:00
var_reference_with_whitespace.vcd
var_reference_without_whitespace.vcd
vcd_var_reference_whitespace.ys	End of file fix	2026-06-23 07:23:41 +02:00
vector_assign.il