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yosys/techlibs/xilinx
..
tests
.gitignore
abc_xc7.box
abc_xc7.lut
abc_xc7_nowide.lut
arith_map.v
brams_init.py
cells_map.v
cells_sim.v
cells_xtra.sh
cells_xtra.v
drams.txt
drams_map.v
ff_map.v
lut_map.v
Makefile.inc
mux_map.v
synth_xilinx.cc
xc6s_brams.txt
xc6s_brams_bb.v
xc6s_brams_map.v
xc7_brams.txt
xc7_brams_bb.v
xc7_brams_map.v