Clifford Wolf bdc316db50 Added $anyseq cell type		2016-10-14 15:24:03 +02:00
..
.gitignore
adff2dff.v
cellhelp.py
cells.lib
Makefile.inc
pmux2mux.v
prep.cc
simcells.v	Added $global_clock verilog syntax support for creating $ff cells	2016-10-14 12:33:56 +02:00
simlib.v	Added $anyseq cell type	2016-10-14 15:24:03 +02:00
synth.cc
techmap.v	Added $ff and $_FF_ cell types	2016-10-12 01:18:39 +02:00